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Searched refs:ctrl_ddr3ch (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/mach-omap2/omap5/
Dhw_data.c671 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
682 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
693 .ctrl_ddr3ch = 0x80808080,
705 .ctrl_ddr3ch = 0x60606080,
717 .ctrl_ddr3ch = 0x60606060,
Dhwinit.c77 writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0); in io_settings_ddr3()
81 writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0); in io_settings_ddr3()
/external/u-boot/arch/arm/include/asm/arch-omap5/
Domap.h247 u32 ctrl_ddr3ch; member