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Searched refs:ctrl_ddrio_0 (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/mach-omap2/omap5/
Dhw_data.c663 .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
672 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
683 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
694 .ctrl_ddrio_0 = 0x00094A40,
706 .ctrl_ddrio_0 = 0x00094A40,
718 .ctrl_ddrio_0 = 0x00094A40,
Dhwinit.c65 writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); in io_settings_lpddr2()
85 writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); in io_settings_ddr3()
/external/u-boot/arch/arm/include/asm/arch-omap5/
Domap.h248 u32 ctrl_ddrio_0; member