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Searched refs:cwl_mask_table (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_init.h66 extern u8 cwl_mask_table[];
Dddr3_training_db.c196 u8 cwl_mask_table[] = { variable
Dddr3_training.c568 data_value = (cwl_mask_table[cwl_val] << 3); in hws_ddr3_tip_init_controller()
1456 (cwl_mask_table[cwl_value] << 12), 0x7000)); in ddr3_tip_freq_set()
1590 val = (cwl_mask_table[cwl_value] << 3) | g_rtt_wr; in ddr3_tip_freq_set()
1633 val = (cwl_mask_table[cwl_value] << 3) | g_rtt_wr; in ddr3_tip_freq_set()