| /external/chromium-trace/catapult/systrace/systrace/test_data/ |
| D | profile-chrome_systrace_perf_chrome_data | 1 …cycles:HG", "weight": 297850, "ts": 196493621870.241, "cpu": 2, "comm": "ksoftirqd/2", "tid": 1410…
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| /external/tensorflow/tensorflow/python/saved_model/ |
| D | load_test.py | 55 dict(testcase_name="ReloadOnce", cycles=1),
56 dict(testcase_name="ReloadTwice", cycles=2),
57 dict(testcase_name="ReloadThrice", cycles=3))
60 def cycle(self, obj, cycles=1, signatures=None): argument
64 for _ in range(cycles):
71 def test_structure_import(self, cycles): argument
77 imported = self.cycle(root, cycles)
81 def test_variables(self, cycles): argument
85 imported = self.cycle(root, cycles)
91 def test_capture_variables(self, cycles): argument
[all …]
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| /external/tensorflow/tensorflow/compiler/xla/service/ |
| D | human_readable_profile_builder.cc | 45 if (op.optimal_seconds == 0 && op.cycles == 0) { in ToString()
51 if (op.cycles > 0 && op.bytes_accessed >= 0) { in ToString()
53 HumanReadableNumBytes(op.bytes_accessed / CyclesToSeconds(op.cycles)), in ToString()
55 double bpc = static_cast<double>(op.bytes_accessed) / op.cycles; in ToString()
56 if (op.bytes_accessed > op.cycles) { in ToString()
66 cumulative_cycles += op.cycles; in ToString()
69 cycles_percent = op.cycles / static_cast<double>(total_cycles_) * 100; in ToString()
84 double nsecs = op.cycles / clock_rate_ghz_; in ToString()
89 op.cycles, cycles_percent_str, CyclesToMicroseconds(op.cycles), in ToString()
115 std::min(double{op.optimal_seconds}, CyclesToSeconds(op.cycles)); in ToString()
[all …]
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| D | human_readable_profile_builder.h | 49 absl::string_view category, int64 cycles, int64 flop_count, in AddOp() argument
53 cycles, flop_count, transcendental_count, in AddOp()
65 int64 cycles; member
72 double CyclesToSeconds(int64 cycles) const { in CyclesToSeconds() argument
73 return cycles / clock_rate_ghz_ / 1e9; in CyclesToSeconds()
75 double CyclesToMicroseconds(int64 cycles) const { in CyclesToMicroseconds() argument
76 return cycles / clock_rate_ghz_ / 1000.0; in CyclesToMicroseconds()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMScheduleA9.td | 78 // No operand cycles
199 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
339 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
460 // Extra latency cycles since wbck is 2 cycles
469 // Extra latency cycles since wbck is 2 cycles
479 // Extra latency cycles since wbck is 4 cycles
488 // Extra latency cycles since wbck is 4 cycles
644 // Extra 1 latency cycle since wbck is 2 cycles
653 // Extra 1 latency cycle since wbck is 2 cycles
694 // FIXME: assumes 2 doubles which requires 2 LS cycles.
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeSchedule3.td | 25 [ 2 // result ready after two cycles
32 // pipeline stages except the execute stage, which takes three cycles. The
38 , InstrStage<3,[EX]>], // three cycles in execute stage
39 [ 4 // result ready after four cycles
45 // stages except the execute stage, which takes 34 cycles. The two
51 , InstrStage<34,[EX]>], // 34 cycles in execute stage
52 [ 35 // result ready after 35 cycles
59 // except the execute stage, which takes two cycles. The two source operands
65 , InstrStage<2,[EX]>], // two cycles in execute stage
66 [ 3 // result ready after three cycles
[all …]
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| D | MBlazeSchedule5.td | 27 [ 2 // result ready after two cycles
42 [ 2 // result ready after two cycles
48 // stages except the memory access stage, which takes 31 cycles. The two
55 , InstrStage<31,[MA]> // 31 cycles in memory access stage
57 [ 33 // result ready after 33 cycles
72 [ 3 // result ready after three cycles
109 [ 4 // result ready after four cycles
114 // except the memory access stage, which takes two cycles. The source
120 , InstrStage<2,[MA]> // two cycles in memory access stage
128 // cycles. The source operands are read during the decode stage and the
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleA9.td | 82 // No operand cycles
203 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
347 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
469 // Extra latency cycles since wbck is 2 cycles
478 // Extra latency cycles since wbck is 2 cycles
488 // Extra latency cycles since wbck is 4 cycles
497 // Extra latency cycles since wbck is 4 cycles
669 // Extra 1 latency cycle since wbck is 2 cycles
678 // Extra 1 latency cycle since wbck is 2 cycles
719 // FIXME: assumes 2 doubles which requires 2 LS cycles.
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleA9.td | 82 // No operand cycles
203 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
347 // FIXME: If address is 64-bit aligned, AGU cycles is 1.
469 // Extra latency cycles since wbck is 2 cycles
478 // Extra latency cycles since wbck is 2 cycles
488 // Extra latency cycles since wbck is 4 cycles
497 // Extra latency cycles since wbck is 4 cycles
669 // Extra 1 latency cycle since wbck is 2 cycles
678 // Extra 1 latency cycle since wbck is 2 cycles
719 // FIXME: assumes 2 doubles which requires 2 LS cycles.
[all …]
|
| /external/u-boot/cmd/ |
| D | time.c | 9 static void report_time(ulong cycles) in report_time() argument
14 total_seconds = cycles / CONFIG_SYS_HZ; in report_time()
15 remainder = cycles % CONFIG_SYS_HZ; in report_time()
29 ulong cycles = 0; in do_time() local
36 retval = cmd_process(0, argc - 1, argv + 1, &repeatable, &cycles); in do_time()
37 report_time(cycles); in do_time()
|
| /external/tensorflow/tensorflow/compiler/jit/ |
| D | xla_cluster_util.cc | 45 string DescribeCycle(const GraphCycles* cycles, const Graph& graph, int src, in DescribeCycle() argument
49 int32 path_size = cycles->FindPath(dst, src, max_path_size, path.data()); in DescribeCycle()
115 GraphCycles* cycles) { in CreateCycleDetectionGraph() argument
119 CHECK_EQ(i, cycles->NewNode()); in CreateCycleDetectionGraph()
145 auto GetOrAddFrameNodeId = [&frame_nodes, cycles](const string& frame_name) { in CreateCycleDetectionGraph()
149 frame_id = cycles->NewNode(); in CreateCycleDetectionGraph()
177 if (!cycles->InsertEdge(src, dst)) { in CreateCycleDetectionGraph()
181 << " edge: " << DescribeCycle(cycles, *graph, src, dst); in CreateCycleDetectionGraph()
191 if (!cycles->InsertEdge(edge->src()->id(), edge->dst()->id())) { in CreateCycleDetectionGraph()
197 DescribeCycle(cycles, *graph, edge->src()->id(), edge->dst()->id())); in CreateCycleDetectionGraph()
[all …]
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| D | xla_cluster_util_test.cc | 47 GraphCycles cycles; in TEST() local
48 TF_ASSERT_OK(CreateCycleDetectionGraph(root.graph(), &cycles).status()); in TEST()
49 EXPECT_FALSE(cycles.ContractEdge(a.node()->id(), b.node()->id())); in TEST()
66 GraphCycles cycles; in TEST() local
67 TF_ASSERT_OK(CreateCycleDetectionGraph(root.graph(), &cycles).status()); in TEST()
68 EXPECT_FALSE(cycles.ContractEdge(a.node()->id(), b.node()->id())); in TEST()
88 GraphCycles cycles; in TEST() local
90 CreateCycleDetectionGraph(root.graph(), &cycles)); in TEST()
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| D | xla_fusion_optimizer.cc | 211 GraphCycles cycles; in Optimize() local
213 CreateCycleDetectionGraph(&graph, &cycles)); in Optimize()
219 &graph, &graph.flib_def(), /*resource_ops_to_ignore=*/{}, &cycles)); in Optimize()
260 for (int to : cycles.Successors(from)) { in Optimize()
292 if (!cycles.ContractEdge(from, to)) continue; in Optimize()
|
| /external/antlr/tool/src/main/java/org/antlr/tool/ |
| D | LeftRecursionCyclesMessage.java | 39 public Collection<? extends Collection<? extends Rule>> cycles; field in LeftRecursionCyclesMessage
41 public LeftRecursionCyclesMessage(Collection<? extends Collection<? extends Rule>> cycles) { in LeftRecursionCyclesMessage() argument
43 this.cycles = cycles; in LeftRecursionCyclesMessage()
49 st.add("listOfCycles", cycles); in toString()
|
| /external/autotest/client/cros/ |
| D | storage.py | 273 storages = self.wait_for_devices(filter_dict, cycles=1,
291 def wait_for_devices(self, storage_filter, time_to_sleep=1, cycles=10, argument
309 '%d secs' % (storage_filter, cycles, time_to_sleep))
315 if cycles == -1:
320 while cycles == -1 or cycle < cycles:
338 (storage_filter, time_to_sleep*cycles))
342 def wait_for_device(self, storage_filter, time_to_sleep=1, cycles=10, argument
367 cycles=cycles,
|
| /external/boringssl/linux-arm/crypto/fipsmodule/ |
| D | sha256-armv4.S | 35 @ lute" terms is ~2250 cycles per 64-byte block or ~35 cycles per
41 @ Cortex A8 core and ~20 cycles per processed byte.
46 @ improvement on Cortex A8 core and ~15.4 cycles per processed byte.
51 @ byte in 12.5 cycles or 23% faster than integer-only code. Snapdragon
52 @ S4 does it in 12.5 cycles too, but it's 50% faster than integer-only
|
| D | sha512-armv4.S | 35 @ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
41 @ Cortex A8 core and ~40 cycles per processed byte.
46 @ improvement on Coxtex A8 core and ~38 cycles per byte.
51 @ one byte in 23.3 cycles or ~60% faster than integer-only code.
|
| /external/boringssl/ios-arm/crypto/fipsmodule/ |
| D | sha256-armv4.S | 34 @ lute" terms is ~2250 cycles per 64-byte block or ~35 cycles per
40 @ Cortex A8 core and ~20 cycles per processed byte.
45 @ improvement on Cortex A8 core and ~15.4 cycles per processed byte.
50 @ byte in 12.5 cycles or 23% faster than integer-only code. Snapdragon
51 @ S4 does it in 12.5 cycles too, but it's 50% faster than integer-only
|
| D | sha512-armv4.S | 34 @ by gcc 3.4 and it spends ~72 clock cycles per byte [on single-issue
40 @ Cortex A8 core and ~40 cycles per processed byte.
45 @ improvement on Coxtex A8 core and ~38 cycles per byte.
50 @ one byte in 23.3 cycles or ~60% faster than integer-only code.
|
| /external/autotest/client/tests/signaltest/src/ |
| D | signaltest.c | 54 unsigned long cycles; member
154 if (!par->id && !(stat->cycles & 0x0F)) in signalthread()
185 stat->cycles++; in signalthread()
188 stat->values[stat->cycles & par->bufmsk] = diff; in signalthread()
190 if (par->max_cycles && par->max_cycles == stat->cycles) in signalthread()
300 stat->cycles, stat->min, stat->act, in print_stat()
301 stat->cycles ? in print_stat()
302 (long)(stat->avg/stat->cycles) : 0, stat->max); in print_stat()
305 while (stat->cycles != stat->cyclesread) { in print_stat()
398 if(max_cycles && stat[0].cycles >= max_cycles) in main()
|
| /external/u-boot/arch/xtensa/lib/ |
| D | time.c | 24 static void delay_cycles(unsigned cycles) in delay_cycles() argument
27 unsigned expiry = get_ccount() + cycles; in delay_cycles()
39 for (i = cycles >> 4U; i > 0; --i) in delay_cycles()
41 fake_ccount += cycles; in delay_cycles()
|
| /external/u-boot/board/keymile/km_arm/ |
| D | kwbimage_256M8_1.cfg | 118 DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1)
119 # bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles
120 # bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles
121 # bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles
122 # bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles
123 # bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles
126 # bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles
127 # bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
130 # bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles
196 # bit 7-4: 2, M_ODT assertion 2 cycles after read start command
[all …]
|
| /external/tensorflow/tensorflow/compiler/xla/tests/ |
| D | xla_hlo_profile_test.cc | 46 int64 cycles; member
109 line, regexp_pattern, &parsed_line.cycles, &parsed_line.cycles_percentage,
247 EXPECT_GT(total_profile.cycles, 0); in XLA_TEST_F()
253 EXPECT_GT(total_profile.cycles, dot_profile.cycles); in XLA_TEST_F()
260 EXPECT_GT(total_profile.cycles, tanh_profile.cycles); in XLA_TEST_F()
352 EXPECT_GT(total_while_body_profile.cycles, 0); in XLA_TEST_F()
356 EXPECT_GT(total_while_body_profile.cycles, multiply_profile.cycles); in XLA_TEST_F()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCScheduleP9.td | 22 // Load latency is 4 or 5 cycles depending on the load. This latency assumes
24 // There are two instructions (lxvl, lxvll) that have a latencty of 6 cycles.
26 // of instructions are 4 or 5 cycles.
29 // A total of 16 cycles to recover from a branch mispredict.
144 // An ALU may take either 2 or 3 cycles to complete the operation.
172 // A DIV unit may take from 5 to 40 cycles to complete.
173 // Some DIV operations may keep the unit busy for up to 8 cycles.
198 // A DP unit may take from 2 to 36 cycles to complete.
199 // Some DP operations keep the unit busy for up to 10 cycles.
297 // Loads can have 4, 5 or 6 cycles of latency.
[all …]
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| /external/webrtc/webrtc/modules/audio_coding/neteq/tools/ |
| D | rtp_analyze.cc | 106 int cycles = -1; in main() local
132 if (cycles == -1) { in main()
135 cycles = 0; in main()
148 cycles++; in main()
157 64.0 * cycles; in main()
|