| /external/llvm/test/MC/ARM/ |
| D | neon-vld-vst-align.s | 5 vld1.8 {d0}, [r4]
6 vld1.8 {d0}, [r4:16]
7 vld1.8 {d0}, [r4:32]
8 vld1.8 {d0}, [r4:64]
9 vld1.8 {d0}, [r4:128]
10 vld1.8 {d0}, [r4:256]
12 @ CHECK: vld1.8 {d0}, [r4] @ encoding: [0x24,0xf9,0x0f,0x07]
14 @ CHECK-ERRORS: vld1.8 {d0}, [r4:16]
17 @ CHECK-ERRORS: vld1.8 {d0}, [r4:32]
19 @ CHECK: vld1.8 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x07]
[all …]
|
| D | vfp-aliases.s | 8 fstmfdd sp!, {d0}
9 fstmead sp!, {d0}
10 fstmdbd sp!, {d0}
11 fstmiad sp!, {d0}
21 fldmiad sp!, {d0}
22 fldmdbd sp!, {d0}
23 fldmead sp!, {d0}
24 fldmfdd sp!, {d0}
26 fstmeax sp!, {d0}
27 fldmfdx sp!, {d0}
[all …]
|
| D | directive-arch_extension-fp.s | 35 vselgt.f64 d0, d0, d0
37 vselge.f64 d0, d0, d0
39 vseleq.f64 d0, d0, d0
41 vselvs.f64 d0, d0, d0
43 vmaxnm.f64 d0, d0, d0
45 vminnm.f64 d0, d0, d0
48 vcvtb.f64.f16 d0, s0
50 vcvtb.f16.f64 s0, d0
52 vcvtt.f64.f16 d0, s0
54 vcvtt.f16.f64 s0, d0
[all …]
|
| D | fullfp16-neon.s | 4 vadd.f16 d0, d1, d2
6 @ ARM: vadd.f16 d0, d1, d2 @ encoding: [0x02,0x0d,0x11,0xf2]
8 @ THUMB: vadd.f16 d0, d1, d2 @ encoding: [0x11,0xef,0x02,0x0d]
11 vsub.f16 d0, d1, d2
13 @ ARM: vsub.f16 d0, d1, d2 @ encoding: [0x02,0x0d,0x31,0xf2]
15 @ THUMB: vsub.f16 d0, d1, d2 @ encoding: [0x31,0xef,0x02,0x0d]
18 vmul.f16 d0, d1, d2
20 @ ARM: vmul.f16 d0, d1, d2 @ encoding: [0x12,0x0d,0x11,0xf3]
22 @ THUMB: vmul.f16 d0, d1, d2 @ encoding: [0x11,0xff,0x12,0x0d]
32 vmla.f16 d0, d1, d2
[all …]
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| D | directive-arch_extension-simd.s | 24 vmaxnm.f64 d0, d0, d0
26 vminnm.f64 d0, d0, d0
33 vcvta.s32.f64 s0, d0
35 vcvta.u32.f64 s0, d0
41 vcvtn.s32.f64 s0, d0
43 vcvtn.u32.f64 s0, d0
49 vcvtp.s32.f64 s0, d0
51 vcvtp.u32.f64 s0, d0
57 vcvtm.s32.f64 s0, d0
59 vcvtm.u32.f64 s0, d0
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | neon-vld-vst-align.s | 5 vld1.8 {d0}, [r4]
6 vld1.8 {d0}, [r4:16]
7 vld1.8 {d0}, [r4:32]
8 vld1.8 {d0}, [r4:64]
9 vld1.8 {d0}, [r4:128]
10 vld1.8 {d0}, [r4:256]
12 @ CHECK: vld1.8 {d0}, [r4] @ encoding: [0x24,0xf9,0x0f,0x07]
14 @ CHECK-ERRORS: vld1.8 {d0}, [r4:16]
17 @ CHECK-ERRORS: vld1.8 {d0}, [r4:32]
19 @ CHECK: vld1.8 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x07]
[all …]
|
| D | directive-arch_extension-fp.s | 35 vselgt.f64 d0, d0, d0
37 vselge.f64 d0, d0, d0
39 vseleq.f64 d0, d0, d0
41 vselvs.f64 d0, d0, d0
43 vmaxnm.f64 d0, d0, d0
45 vminnm.f64 d0, d0, d0
48 vcvtb.f64.f16 d0, s0
50 vcvtb.f16.f64 s0, d0
52 vcvtt.f64.f16 d0, s0
54 vcvtt.f16.f64 s0, d0
[all …]
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| D | neon-complex.s | 22 vcmla.f16 d0, d1, d2, #0
34 vcmla.f32 d0, d1, d2, #0
46 vcmla.f32 d0, d1, d2, #90
51 vcmla.f32 d0, d1, d2, #180
56 vcmla.f32 d0, d1, d2, #270
63 vcmla.f32 d0, d1, d2, #-90
66 vcmla.f32 d0, d1, d2, #1
69 vcmla.f32 d0, d1, d2, #360
76 vcadd.f16 d0, d1, d2, #90
88 vcadd.f32 d0, d1, d2, #90
[all …]
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| D | fullfp16-neon.s | 4 vadd.f16 d0, d1, d2
6 @ ARM: vadd.f16 d0, d1, d2 @ encoding: [0x02,0x0d,0x11,0xf2]
8 @ THUMB: vadd.f16 d0, d1, d2 @ encoding: [0x11,0xef,0x02,0x0d]
11 vsub.f16 d0, d1, d2
13 @ ARM: vsub.f16 d0, d1, d2 @ encoding: [0x02,0x0d,0x31,0xf2]
15 @ THUMB: vsub.f16 d0, d1, d2 @ encoding: [0x31,0xef,0x02,0x0d]
18 vmul.f16 d0, d1, d2
20 @ ARM: vmul.f16 d0, d1, d2 @ encoding: [0x12,0x0d,0x11,0xf3]
22 @ THUMB: vmul.f16 d0, d1, d2 @ encoding: [0x11,0xff,0x12,0x0d]
32 vmla.f16 d0, d1, d2
[all …]
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| D | directive-arch_extension-simd.s | 24 vmaxnm.f64 d0, d0, d0
26 vminnm.f64 d0, d0, d0
33 vcvta.s32.f64 s0, d0
35 vcvta.u32.f64 s0, d0
41 vcvtn.s32.f64 s0, d0
43 vcvtn.u32.f64 s0, d0
49 vcvtp.s32.f64 s0, d0
51 vcvtp.u32.f64 s0, d0
57 vcvtm.s32.f64 s0, d0
59 vcvtm.u32.f64 s0, d0
[all …]
|
| D | vfp-aliases.s | 8 fstmeax sp!, {d0}
9 fldmfdx sp!, {d0}
11 fstmfdx sp!, {d0}
12 fldmeax sp!, {d0}
15 @ CHECK: fstmiax sp!, {d0}
16 @ CHECK: fldmiax sp!, {d0}
17 @ CHECK: fstmdbx sp!, {d0}
18 @ CHECK: fldmdbx sp!, {d0}
20 fstmiaxcs r0, {d0}
21 fstmiaxhs r0, {d0}
[all …]
|
| /external/libaom/libaom/av1/common/x86/ |
| D | intra_edge_sse4.c | 56 __m128i d0 = _mm_shuffle_epi8(in0, shuf0); in av1_filter_intra_edge_sse4_1() local
58 d0 = _mm_maddubs_epi16(d0, coef0); in av1_filter_intra_edge_sse4_1()
60 d0 = _mm_hadd_epi16(d0, d1); in av1_filter_intra_edge_sse4_1()
62 d0 = _mm_add_epi16(d0, eight); in av1_filter_intra_edge_sse4_1()
63 d0 = _mm_srai_epi16(d0, 4); in av1_filter_intra_edge_sse4_1()
64 d0 = _mm_packus_epi16(d0, d0); in av1_filter_intra_edge_sse4_1()
68 out0 = _mm_blendv_epi8(out0, d0, mask); in av1_filter_intra_edge_sse4_1()
87 __m128i d0 = _mm_shuffle_epi8(in0, shuf_a); in av1_filter_intra_edge_sse4_1() local
91 d0 = _mm_maddubs_epi16(d0, coef0); in av1_filter_intra_edge_sse4_1()
95 d0 = _mm_hadd_epi16(d0, d1); in av1_filter_intra_edge_sse4_1()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/ |
| D | foreach-eval.td | 6 def d0;
13 dag r1 = !foreach(tmp, d, !subst(d1, d0, !subst(d2, d0,
14 !subst(d3, d0,
15 !subst(d4, d0, tmp)))));
18 !foreach(tmp, tmp2, !subst(d1, d0,
19 !subst(d2, d0,
20 !subst(d3, d0,
21 !subst(d4, d0, tmp))))));
25 // CHECK: dag r1 = (d0 d0, d0, d0, d0);
26 // CHECK: list<dag> r2 = [(d0 d0, d0, d0, d0)];
[all …]
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| /external/libavc/common/arm/ |
| D | ih264_inter_pred_luma_horz_hpel_vert_qpel_a9q.s | 152 vext.8 d5, d0, d1, #5
153 vaddl.u8 q3, d0, d5
155 vext.8 d2, d0, d1, #2
156 vext.8 d3, d0, d1, #3
158 vext.8 d4, d0, d1, #4
160 vext.8 d1, d0, d1, #1
164 vext.8 d5, d0, d1, #5
165 vaddl.u8 q4, d0, d5
166 vext.8 d2, d0, d1, #2
167 vext.8 d3, d0, d1, #3
[all …]
|
| /external/u-boot/arch/m68k/cpu/mcf5445x/ |
| D | start.S | 23 moveml %d0-%d7/%a0-%a6,%sp@;
26 moveml %sp@,%d0-%d7/%a0-%a6; \
128 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
129 movec %d0, %RAMBAR1
136 move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
137 movec %d0, %VBR
139 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
140 movec %d0, %RAMBAR1
143 move.l #0, %d0
146 move.l %d0, (%a1)
[all …]
|
| /external/libavc/encoder/arm/ |
| D | ih264e_half_pel.s | 88 vmov.i8 d0, #5
145 vmlsl.u8 q4, d31, d0 @// a0 + a5 + 20a2 + 20a3 - 5a1 (column1,row0)
147 vmlsl.u8 q5, d30, d0 @// a0 + a5 + 20a2 + 20a3 - 5a1 (column2,row0)
149 vmlsl.u8 q6, d29, d0 @// a0 + a5 + 20a2 + 20a3 - 5a1 (column3,row0)
151 vmlsl.u8 q7, d28, d0 @// a0 + a5 + 20a2 + 20a3 - 5a1 (column1,row1)
154 vmlsl.u8 q8, d27, d0 @// a0 + a5 + 20a2 + 20a3 - 5a1 (column2,row1)
156 vmlsl.u8 q9, d26, d0 @// a0 + a5 + 20a2 + 20a3 - 5a1 (column3,row1)
158 vmlsl.u8 q4, d31, d0 @// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column1,row0)
160 vmlsl.u8 q5, d30, d0 @// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column2,row0)
162 vmlsl.u8 q6, d29, d0 @// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column3,row0)
[all …]
|
| /external/libmpeg2/common/arm/ |
| D | impeg2_mem_func.s | 103 vdup.8 d0, r1 @//r1 is the 8-bit value to be set into
105 vst1.8 {d0}, [r0], r2 @//Store the row 1
106 vst1.8 {d0}, [r0], r2 @//Store the row 2
107 vst1.8 {d0}, [r0], r2 @//Store the row 3
108 vst1.8 {d0}, [r0], r2 @//Store the row 4
109 vst1.8 {d0}, [r0], r2 @//Store the row 5
110 vst1.8 {d0}, [r0], r2 @//Store the row 6
111 vst1.8 {d0}, [r0], r2 @//Store the row 7
112 vst1.8 {d0}, [r0], r2 @//Store the row 8
155 vst1.16 {d0, d1} , [r0]! @row1
[all …]
|
| D | impeg2_inter_pred.s | 109 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
110 vst1.8 {d0, d1}, [r5], r3 @Store and increment dst
113 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
114 vst1.8 {d0, d1}, [r5], r3 @Store and increment dst
115 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
116 vst1.8 {d0, d1}, [r5], r3 @Store and increment dst
117 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
118 vst1.8 {d0, d1}, [r5], r3 @Store and increment dst
119 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
120 vst1.8 {d0, d1}, [r5], r3 @Store and increment dst
[all …]
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| D | ideint_cac_a9.s | 151 vadd.u32 d21, d0, d1
161 vabd.u8 d0, d0, d1
167 vcge.u8 d1, d0, d9
168 vand.u8 d0, d0, d1
169 @ d0 now contains 8 absolute diff of sums above the threshold
172 vpaddl.u8 d0, d0
173 vshl.u16 d0, d0, #2
176 vadd.u16 d20, d0, d20
182 vrhadd.u8 d0, d28, d29
184 vrhadd.u8 d0, d0, d2
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | neont-VLD-reencoding.txt | 12 # CHECK: vld1.8 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x00]
13 # CHECK: vld1.8 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x00]
14 # CHECK: vld1.8 {d0[2]}, [r0], r0 @ encoding: [0xa0,0xf9,0x40,0x00]
15 # CHECK: vld1.8 {d0[3]}, [r0], r0 @ encoding: [0xa0,0xf9,0x60,0x00]
16 # CHECK: vld1.8 {d0[4]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x00]
17 # CHECK: vld1.8 {d0[5]}, [r0], r0 @ encoding: [0xa0,0xf9,0xa0,0x00]
18 # CHECK: vld1.8 {d0[6]}, [r0], r0 @ encoding: [0xa0,0xf9,0xc0,0x00]
19 # CHECK: vld1.8 {d0[7]}, [r0], r0 @ encoding: [0xa0,0xf9,0xe0,0x00]
30 # CHECK: vld1.16 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x04]
31 # CHECK: vld1.16 {d0[0]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x10,0x04]
[all …]
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | neont-VLD-reencoding.txt | 12 # CHECK: vld1.8 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x00]
13 # CHECK: vld1.8 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x00]
14 # CHECK: vld1.8 {d0[2]}, [r0], r0 @ encoding: [0xa0,0xf9,0x40,0x00]
15 # CHECK: vld1.8 {d0[3]}, [r0], r0 @ encoding: [0xa0,0xf9,0x60,0x00]
16 # CHECK: vld1.8 {d0[4]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x00]
17 # CHECK: vld1.8 {d0[5]}, [r0], r0 @ encoding: [0xa0,0xf9,0xa0,0x00]
18 # CHECK: vld1.8 {d0[6]}, [r0], r0 @ encoding: [0xa0,0xf9,0xc0,0x00]
19 # CHECK: vld1.8 {d0[7]}, [r0], r0 @ encoding: [0xa0,0xf9,0xe0,0x00]
30 # CHECK: vld1.16 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x04]
31 # CHECK: vld1.16 {d0[0]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x10,0x04]
[all …]
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| /external/libffi/src/m68k/ |
| D | sysv.S | 82 move.l %d0,%a1
111 move.l %d0,(%a1)
117 move.l %d0,(%a1)
127 move.l %d0,(%a1)
137 move.l %d0,(%a1)+
148 move.l %d0,(%a1)+
158 move.l %d0,(%a1)
167 move.b %d0,(%a1)
173 move.w %d0,(%a1)
181 ext.w %d0
[all …]
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| /external/python/cpython2/Modules/_ctypes/libffi/src/m68k/ |
| D | sysv.S | 82 move.l %d0,%a1
111 move.l %d0,(%a1)
117 move.l %d0,(%a1)
127 move.l %d0,(%a1)
137 move.l %d0,(%a1)+
148 move.l %d0,(%a1)+
158 move.l %d0,(%a1)
167 move.b %d0,(%a1)
173 move.w %d0,(%a1)
181 ext.w %d0
[all …]
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| /external/u-boot/arch/m68k/cpu/mcf5227x/ |
| D | start.S | 18 moveml %d0-%d7/%a0-%a6,%sp@;
21 moveml %sp@,%d0-%d7/%a0-%a6; \
108 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
109 movec %d0, %RAMBAR1 /* init Rambar */
177 move.l #1000, %d0
180 subq.l #1, %d0
188 move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
190 move.l %d0, (%a2)
191 move.l %d0, (%a2)
194 move.l #(CONFIG_SYS_SDRAM_CTRL), %d0
[all …]
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| /external/libvpx/libvpx/vpx_dsp/arm/ |
| D | highbd_vpx_convolve_avg_neon.c | 29 uint16x4_t s0, s1, d0, d1; in vpx_highbd_convolve_avg_neon() local
33 d0 = vld1_u16(dst); in vpx_highbd_convolve_avg_neon()
39 d01 = vcombine_u16(d0, d1); in vpx_highbd_convolve_avg_neon()
48 uint16x8_t s0, s1, d0, d1; in vpx_highbd_convolve_avg_neon() local
51 d0 = vld1q_u16(dst); in vpx_highbd_convolve_avg_neon()
57 d0 = vrhaddq_u16(s0, d0); in vpx_highbd_convolve_avg_neon()
60 vst1q_u16(dst, d0); in vpx_highbd_convolve_avg_neon()
94 uint16x8_t s0, s1, s2, s3, d0, d1, d2, d3; in vpx_highbd_convolve_avg_neon() local
100 d0 = vld1q_u16(dst); in vpx_highbd_convolve_avg_neon()
106 d0 = vrhaddq_u16(s0, d0); in vpx_highbd_convolve_avg_neon()
[all …]
|