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Searched refs:dccRamBaseAlign (Results 1 – 4 of 4) sorted by relevance

/external/mesa3d/src/amd/addrlib/r800/
Dciaddrlib.cpp243 pOut->dccRamBaseAlign = pIn->tileInfo.banks * in HwlComputeDccInfo()
249 ADDR_ASSERT(IsPow2(pOut->dccRamBaseAlign)); in HwlComputeDccInfo()
251 if (0 == (pOut->dccRamSize & (pOut->dccRamBaseAlign - 1))) in HwlComputeDccInfo()
/external/mesa3d/src/amd/common/
Dac_surface.c353 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign); in gfx6_compute_level()
959 surf->dcc_alignment = dout.dccRamBaseAlign; in gfx9_compute_miptree()
/external/mesa3d/src/amd/addrlib/
Daddrinterface.h2276 UINT_64 dccRamBaseAlign; ///< Base alignment of dcc key member
3325 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key member
/external/mesa3d/src/amd/addrlib/gfx9/
Dgfx9addrlib.cpp565 pOut->dccRamBaseAlign = numPipeTotal * m_pipeInterleaveBytes; in HwlComputeDccInfo()
566 pOut->dccRamSize = PowTwoAlign((pIn->dataSurfaceSize / 256), pOut->dccRamBaseAlign); in HwlComputeDccInfo()
644 pOut->dccRamBaseAlign = Max(numCompressBlkPerMetaBlk, sizeAlign); in HwlComputeDccInfo()
648 pOut->dccRamBaseAlign = Max(pOut->dccRamBaseAlign, GetBlockSize(pIn->swizzleMode)); in HwlComputeDccInfo()