Searched refs:dcc_offset (Results 1 – 14 of 14) sorted by relevance
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_clear.c | 198 uint64_t dcc_offset, clear_size; in vi_dcc_clear_level() local
204 dcc_offset = 0; in vi_dcc_clear_level()
207 dcc_offset = rtex->dcc_offset; in vi_dcc_clear_level()
227 dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset; in vi_dcc_clear_level()
232 si_clear_buffer(&sctx->b.b, dcc_buffer, dcc_offset, clear_size, in vi_dcc_clear_level()
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| D | si_blit.c | 469 assert(rtex->dcc_offset); in si_blit_decompress_color()
534 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset) in si_decompress_color_texture()
597 if (!tex->dcc_offset) in si_check_render_feedback_texture()
842 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) { in si_decompress_subresource()
1302 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) { in si_flush_resource()
1318 if (!rtex->dcc_offset) in si_decompress_dcc()
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| D | si_descriptors.c | 354 tex->dcc_offset; in si_set_mutable_tex_desc_fields()
357 meta_va += base_level_info->dcc_offset; in si_set_mutable_tex_desc_fields()
390 if (tex->dcc_offset) in si_set_mutable_tex_desc_fields()
479 (rtex->cmask.size || rtex->dcc_offset)); in color_needs_decompression()
528 if (rtex->dcc_offset && in si_set_sampler_view()
2334 if (rtex->dcc_offset && in si_make_texture_handle_resident()
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| D | si_state.c | 3024 tex->dcc_offset) >> 8; in si_emit_framebuffer_state()
3031 if (tex->dcc_offset) in si_emit_framebuffer_state()
3080 cb_dcc_base += level_info->dcc_offset >> 8; in si_emit_framebuffer_state()
3730 if (tex->dcc_offset) { in si_make_texture_descriptor()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | r600_texture.c | 427 return rtex->dcc_offset && in r600_can_disable_dcc()
441 rtex->dcc_offset = 0; in r600_texture_discard_dcc()
569 assert(!rtex->dcc_offset); in r600_reallocate_texture_inplace()
632 desc[7] = rtex->dcc_offset >> 8; in si_query_opaque_metadata()
663 rtex->dcc_offset = (uint64_t)desc[7] << 8; in si_apply_opaque_metadata()
670 rtex->dcc_offset = 0; in si_apply_opaque_metadata()
717 if (usage & PIPE_HANDLE_USAGE_WRITE && rtex->dcc_offset) { in r600_texture_get_handle()
726 (rtex->cmask.size || rtex->dcc_offset)) { in r600_texture_get_handle()
1100 if (rtex->dcc_offset) { in si_print_texture_info()
1103 rtex->dcc_offset, rtex->surface.dcc_size, in si_print_texture_info()
[all …]
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| D | r600_pipe_common.h | 220 uint64_t dcc_offset; /* 0 = disabled */ member
661 return tex->dcc_offset && level < tex->surface.num_dcc_levels; in vi_dcc_enabled()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_image.c | 268 meta_va = gpu_address + image->dcc_offset; in si_set_mutable_tex_desc_fields()
270 meta_va += base_level_info->dcc_offset; in si_set_mutable_tex_desc_fields()
301 if (image->dcc_offset) in si_set_mutable_tex_desc_fields()
482 if (image->dcc_offset) { in si_make_texture_descriptor()
609 desc[7] = image->dcc_offset >> 8; in radv_query_opaque_metadata()
797 image->dcc_offset = align64(image->size, image->surface.dcc_alignment); in radv_image_alloc_dcc()
799 image->clear_value_offset = image->dcc_offset + image->surface.dcc_size; in radv_image_alloc_dcc()
801 image->size = image->dcc_offset + image->surface.dcc_size + 16; in radv_image_alloc_dcc()
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| D | radv_meta_fast_clear.c | 775 image->offset + image->dcc_offset, in radv_decompress_dcc_compute()
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| D | radv_private.h | 1379 uint64_t dcc_offset; member
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| D | radv_meta_clear.c | 1024 iview->image->offset + iview->image->dcc_offset, in emit_fast_color_clear()
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| D | radv_device.c | 3108 if (iview->image->dcc_offset) in radv_initialise_color_surface()
3158 va += iview->image->dcc_offset; in radv_initialise_color_surface()
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| D | radv_cmd_buffer.c | 3999 image->offset + image->dcc_offset, in radv_initialize_dcc()
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| /external/mesa3d/src/amd/common/ |
| D | ac_surface.h | 75 uint32_t dcc_offset; /* relative offset within DCC mip tree */ member
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| D | ac_surface.c | 333 surf_level->dcc_offset = 0; in gfx6_compute_level()
349 surf_level->dcc_offset = surf->dcc_size; in gfx6_compute_level()
352 surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize; in gfx6_compute_level()
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