1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * (C) Copyright 2015 Google, Inc 4 */ 5 6 #ifndef _ASM_ARCH_DDR_RK3288_H 7 #define _ASM_ARCH_DDR_RK3288_H 8 9 struct rk3288_ddr_pctl { 10 u32 scfg; 11 u32 sctl; 12 u32 stat; 13 u32 intrstat; 14 u32 reserved0[12]; 15 u32 mcmd; 16 u32 powctl; 17 u32 powstat; 18 u32 cmdtstat; 19 u32 tstaten; 20 u32 reserved1[3]; 21 u32 mrrcfg0; 22 u32 mrrstat0; 23 u32 mrrstat1; 24 u32 reserved2[4]; 25 u32 mcfg1; 26 u32 mcfg; 27 u32 ppcfg; 28 u32 mstat; 29 u32 lpddr2zqcfg; 30 u32 reserved3; 31 u32 dtupdes; 32 u32 dtuna; 33 u32 dtune; 34 u32 dtuprd0; 35 u32 dtuprd1; 36 u32 dtuprd2; 37 u32 dtuprd3; 38 u32 dtuawdt; 39 u32 reserved4[3]; 40 u32 togcnt1u; 41 u32 tinit; 42 u32 trsth; 43 u32 togcnt100n; 44 u32 trefi; 45 u32 tmrd; 46 u32 trfc; 47 u32 trp; 48 u32 trtw; 49 u32 tal; 50 u32 tcl; 51 u32 tcwl; 52 u32 tras; 53 u32 trc; 54 u32 trcd; 55 u32 trrd; 56 u32 trtp; 57 u32 twr; 58 u32 twtr; 59 u32 texsr; 60 u32 txp; 61 u32 txpdll; 62 u32 tzqcs; 63 u32 tzqcsi; 64 u32 tdqs; 65 u32 tcksre; 66 u32 tcksrx; 67 u32 tcke; 68 u32 tmod; 69 u32 trstl; 70 u32 tzqcl; 71 u32 tmrr; 72 u32 tckesr; 73 u32 tdpd; 74 u32 reserved5[14]; 75 u32 ecccfg; 76 u32 ecctst; 77 u32 eccclr; 78 u32 ecclog; 79 u32 reserved6[28]; 80 u32 dtuwactl; 81 u32 dturactl; 82 u32 dtucfg; 83 u32 dtuectl; 84 u32 dtuwd0; 85 u32 dtuwd1; 86 u32 dtuwd2; 87 u32 dtuwd3; 88 u32 dtuwdm; 89 u32 dturd0; 90 u32 dturd1; 91 u32 dturd2; 92 u32 dturd3; 93 u32 dtulfsrwd; 94 u32 dtulfsrrd; 95 u32 dtueaf; 96 u32 dfitctrldelay; 97 u32 dfiodtcfg; 98 u32 dfiodtcfg1; 99 u32 dfiodtrankmap; 100 u32 dfitphywrdata; 101 u32 dfitphywrlat; 102 u32 reserved7[2]; 103 u32 dfitrddataen; 104 u32 dfitphyrdlat; 105 u32 reserved8[2]; 106 u32 dfitphyupdtype0; 107 u32 dfitphyupdtype1; 108 u32 dfitphyupdtype2; 109 u32 dfitphyupdtype3; 110 u32 dfitctrlupdmin; 111 u32 dfitctrlupdmax; 112 u32 dfitctrlupddly; 113 u32 reserved9; 114 u32 dfiupdcfg; 115 u32 dfitrefmski; 116 u32 dfitctrlupdi; 117 u32 reserved10[4]; 118 u32 dfitrcfg0; 119 u32 dfitrstat0; 120 u32 dfitrwrlvlen; 121 u32 dfitrrdlvlen; 122 u32 dfitrrdlvlgateen; 123 u32 dfiststat0; 124 u32 dfistcfg0; 125 u32 dfistcfg1; 126 u32 reserved11; 127 u32 dfitdramclken; 128 u32 dfitdramclkdis; 129 u32 dfistcfg2; 130 u32 dfistparclr; 131 u32 dfistparlog; 132 u32 reserved12[3]; 133 u32 dfilpcfg0; 134 u32 reserved13[3]; 135 u32 dfitrwrlvlresp0; 136 u32 dfitrwrlvlresp1; 137 u32 dfitrwrlvlresp2; 138 u32 dfitrrdlvlresp0; 139 u32 dfitrrdlvlresp1; 140 u32 dfitrrdlvlresp2; 141 u32 dfitrwrlvldelay0; 142 u32 dfitrwrlvldelay1; 143 u32 dfitrwrlvldelay2; 144 u32 dfitrrdlvldelay0; 145 u32 dfitrrdlvldelay1; 146 u32 dfitrrdlvldelay2; 147 u32 dfitrrdlvlgatedelay0; 148 u32 dfitrrdlvlgatedelay1; 149 u32 dfitrrdlvlgatedelay2; 150 u32 dfitrcmd; 151 u32 reserved14[46]; 152 u32 ipvr; 153 u32 iptr; 154 }; 155 check_member(rk3288_ddr_pctl, iptr, 0x03fc); 156 157 struct rk3288_ddr_publ_datx { 158 u32 dxgcr; 159 u32 dxgsr[2]; 160 u32 dxdllcr; 161 u32 dxdqtr; 162 u32 dxdqstr; 163 u32 reserved[10]; 164 }; 165 166 struct rk3288_ddr_publ { 167 u32 ridr; 168 u32 pir; 169 u32 pgcr; 170 u32 pgsr; 171 u32 dllgcr; 172 u32 acdllcr; 173 u32 ptr[3]; 174 u32 aciocr; 175 u32 dxccr; 176 u32 dsgcr; 177 u32 dcr; 178 u32 dtpr[3]; 179 u32 mr[4]; 180 u32 odtcr; 181 u32 dtar; 182 u32 dtdr[2]; 183 u32 reserved1[24]; 184 u32 dcuar; 185 u32 dcudr; 186 u32 dcurr; 187 u32 dculr; 188 u32 dcugcr; 189 u32 dcutpr; 190 u32 dcusr[2]; 191 u32 reserved2[8]; 192 u32 bist[17]; 193 u32 reserved3[15]; 194 u32 zq0cr[2]; 195 u32 zq0sr[2]; 196 u32 zq1cr[2]; 197 u32 zq1sr[2]; 198 u32 zq2cr[2]; 199 u32 zq2sr[2]; 200 u32 zq3cr[2]; 201 u32 zq3sr[2]; 202 struct rk3288_ddr_publ_datx datx8[4]; 203 }; 204 check_member(rk3288_ddr_publ, datx8[3].dxdqstr, 0x0294); 205 206 struct rk3288_msch { 207 u32 coreid; 208 u32 revisionid; 209 u32 ddrconf; 210 u32 ddrtiming; 211 u32 ddrmode; 212 u32 readlatency; 213 u32 reserved1[8]; 214 u32 activate; 215 u32 devtodev; 216 }; 217 check_member(rk3288_msch, devtodev, 0x003c); 218 219 /* PCT_DFISTCFG0 */ 220 #define DFI_INIT_START (1 << 0) 221 222 /* PCT_DFISTCFG1 */ 223 #define DFI_DRAM_CLK_SR_EN (1 << 0) 224 #define DFI_DRAM_CLK_DPD_EN (1 << 1) 225 226 /* PCT_DFISTCFG2 */ 227 #define DFI_PARITY_INTR_EN (1 << 0) 228 #define DFI_PARITY_EN (1 << 1) 229 230 /* PCT_DFILPCFG0 */ 231 #define TLP_RESP_TIME_SHIFT 16 232 #define LP_SR_EN (1 << 8) 233 #define LP_PD_EN (1 << 0) 234 235 /* PCT_DFITCTRLDELAY */ 236 #define TCTRL_DELAY_TIME_SHIFT 0 237 238 /* PCT_DFITPHYWRDATA */ 239 #define TPHY_WRDATA_TIME_SHIFT 0 240 241 /* PCT_DFITPHYRDLAT */ 242 #define TPHY_RDLAT_TIME_SHIFT 0 243 244 /* PCT_DFITDRAMCLKDIS */ 245 #define TDRAM_CLK_DIS_TIME_SHIFT 0 246 247 /* PCT_DFITDRAMCLKEN */ 248 #define TDRAM_CLK_EN_TIME_SHIFT 0 249 250 /* PCTL_DFIODTCFG */ 251 #define RANK0_ODT_WRITE_SEL (1 << 3) 252 #define RANK1_ODT_WRITE_SEL (1 << 11) 253 254 /* PCTL_DFIODTCFG1 */ 255 #define ODT_LEN_BL8_W_SHIFT 16 256 257 /* PUBL_ACDLLCR */ 258 #define ACDLLCR_DLLDIS (1 << 31) 259 #define ACDLLCR_DLLSRST (1 << 30) 260 261 /* PUBL_DXDLLCR */ 262 #define DXDLLCR_DLLDIS (1 << 31) 263 #define DXDLLCR_DLLSRST (1 << 30) 264 265 /* PUBL_DLLGCR */ 266 #define DLLGCR_SBIAS (1 << 30) 267 268 /* PUBL_DXGCR */ 269 #define DQSRTT (1 << 9) 270 #define DQRTT (1 << 10) 271 272 /* PIR */ 273 #define PIR_INIT (1 << 0) 274 #define PIR_DLLSRST (1 << 1) 275 #define PIR_DLLLOCK (1 << 2) 276 #define PIR_ZCAL (1 << 3) 277 #define PIR_ITMSRST (1 << 4) 278 #define PIR_DRAMRST (1 << 5) 279 #define PIR_DRAMINIT (1 << 6) 280 #define PIR_QSTRN (1 << 7) 281 #define PIR_RVTRN (1 << 8) 282 #define PIR_ICPC (1 << 16) 283 #define PIR_DLLBYP (1 << 17) 284 #define PIR_CTLDINIT (1 << 18) 285 #define PIR_CLRSR (1 << 28) 286 #define PIR_LOCKBYP (1 << 29) 287 #define PIR_ZCALBYP (1 << 30) 288 #define PIR_INITBYP (1u << 31) 289 290 /* PGCR */ 291 #define PGCR_DFTLMT_SHIFT 3 292 #define PGCR_DFTCMP_SHIFT 2 293 #define PGCR_DQSCFG_SHIFT 1 294 #define PGCR_ITMDMD_SHIFT 0 295 296 /* PGSR */ 297 #define PGSR_IDONE (1 << 0) 298 #define PGSR_DLDONE (1 << 1) 299 #define PGSR_ZCDONE (1 << 2) 300 #define PGSR_DIDONE (1 << 3) 301 #define PGSR_DTDONE (1 << 4) 302 #define PGSR_DTERR (1 << 5) 303 #define PGSR_DTIERR (1 << 6) 304 #define PGSR_DFTERR (1 << 7) 305 #define PGSR_RVERR (1 << 8) 306 #define PGSR_RVEIRR (1 << 9) 307 308 /* PTR0 */ 309 #define PRT_ITMSRST_SHIFT 18 310 #define PRT_DLLLOCK_SHIFT 6 311 #define PRT_DLLSRST_SHIFT 0 312 313 /* PTR1 */ 314 #define PRT_DINIT0_SHIFT 0 315 #define PRT_DINIT1_SHIFT 19 316 317 /* PTR2 */ 318 #define PRT_DINIT2_SHIFT 0 319 #define PRT_DINIT3_SHIFT 17 320 321 /* DCR */ 322 #define DDRMD_LPDDR 0 323 #define DDRMD_DDR 1 324 #define DDRMD_DDR2 2 325 #define DDRMD_DDR3 3 326 #define DDRMD_LPDDR2_LPDDR3 4 327 #define DDRMD_MASK 7 328 #define DDRMD_SHIFT 0 329 #define PDQ_MASK 7 330 #define PDQ_SHIFT 4 331 332 /* DXCCR */ 333 #define DQSNRES_MASK 0xf 334 #define DQSNRES_SHIFT 8 335 #define DQSRES_MASK 0xf 336 #define DQSRES_SHIFT 4 337 338 /* DTPR */ 339 #define TDQSCKMAX_SHIFT 27 340 #define TDQSCKMAX_MASK 7 341 #define TDQSCK_SHIFT 24 342 #define TDQSCK_MASK 7 343 344 /* DSGCR */ 345 #define DQSGX_SHIFT 5 346 #define DQSGX_MASK 7 347 #define DQSGE_SHIFT 8 348 #define DQSGE_MASK 7 349 350 /* SCTL */ 351 #define INIT_STATE 0 352 #define CFG_STATE 1 353 #define GO_STATE 2 354 #define SLEEP_STATE 3 355 #define WAKEUP_STATE 4 356 357 /* STAT */ 358 #define LP_TRIG_SHIFT 4 359 #define LP_TRIG_MASK 7 360 #define PCTL_STAT_MSK 7 361 #define INIT_MEM 0 362 #define CONFIG 1 363 #define CONFIG_REQ 2 364 #define ACCESS 3 365 #define ACCESS_REQ 4 366 #define LOW_POWER 5 367 #define LOW_POWER_ENTRY_REQ 6 368 #define LOW_POWER_EXIT_REQ 7 369 370 /* ZQCR*/ 371 #define PD_OUTPUT_SHIFT 0 372 #define PU_OUTPUT_SHIFT 5 373 #define PD_ONDIE_SHIFT 10 374 #define PU_ONDIE_SHIFT 15 375 #define ZDEN_SHIFT 28 376 377 /* DDLGCR */ 378 #define SBIAS_BYPASS (1 << 23) 379 380 /* MCFG */ 381 #define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24 382 #define PD_IDLE_SHIFT 8 383 #define MDDR_EN (2 << 22) 384 #define LPDDR2_EN (3 << 22) 385 #define DDR2_EN (0 << 5) 386 #define DDR3_EN (1 << 5) 387 #define LPDDR2_S2 (0 << 6) 388 #define LPDDR2_S4 (1 << 6) 389 #define MDDR_LPDDR2_BL_2 (0 << 20) 390 #define MDDR_LPDDR2_BL_4 (1 << 20) 391 #define MDDR_LPDDR2_BL_8 (2 << 20) 392 #define MDDR_LPDDR2_BL_16 (3 << 20) 393 #define DDR2_DDR3_BL_4 0 394 #define DDR2_DDR3_BL_8 1 395 #define TFAW_SHIFT 18 396 #define PD_EXIT_SLOW (0 << 17) 397 #define PD_EXIT_FAST (1 << 17) 398 #define PD_TYPE_SHIFT 16 399 #define BURSTLENGTH_SHIFT 20 400 401 /* POWCTL */ 402 #define POWER_UP_START (1 << 0) 403 404 /* POWSTAT */ 405 #define POWER_UP_DONE (1 << 0) 406 407 /* MCMD */ 408 enum { 409 DESELECT_CMD = 0, 410 PREA_CMD, 411 REF_CMD, 412 MRS_CMD, 413 ZQCS_CMD, 414 ZQCL_CMD, 415 RSTL_CMD, 416 MRR_CMD = 8, 417 DPDE_CMD, 418 }; 419 420 #define LPDDR2_MA_SHIFT 4 421 #define LPDDR2_MA_MASK 0xff 422 #define LPDDR2_OP_SHIFT 12 423 #define LPDDR2_OP_MASK 0xff 424 425 #define START_CMD (1u << 31) 426 427 /* 428 * DDRCONF 429 * [5:4] row(13+n) 430 * [1:0] col(9+n), assume bw=2 431 */ 432 #define DDRCONF_ROW_SHIFT 4 433 #define DDRCONF_COL_SHIFT 0 434 435 /* DEVTODEV */ 436 #define BUSWRTORD_SHIFT 4 437 #define BUSRDTOWR_SHIFT 2 438 #define BUSRDTORD_SHIFT 0 439 440 /* mr1 for ddr3 */ 441 #define DDR3_DLL_DISABLE 1 442 443 #endif 444