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Searched refs:ddr3_read_pup_reg (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_hw_training.c597 u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup) in ddr3_read_pup_reg() function
729 val = ddr3_read_pup_reg( in ddr3_save_training()
740 val = ddr3_read_pup_reg( in ddr3_save_training()
751 val = ddr3_read_pup_reg( in ddr3_save_training()
1054 reg = ddr3_read_pup_reg(PUP_RL_MODE, cs, pup); in ddr3_get_min_max_rl_phase()
Dddr3_write_leveling.c115 ddr3_read_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw()
126 ddr3_read_pup_reg(PUP_WL_MODE + 0x1, in ddr3_write_leveling_hw()
436 reg = ddr3_read_pup_reg(PUP_WL_MODE, cs, pup); in ddr3_wl_supplement()
538 ddr3_read_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw_reg_dimm()
562 ddr3_read_pup_reg(PUP_WL_MODE + 0x1, in ddr3_write_leveling_hw_reg_dimm()
Dddr3_read_leveling.c106 ddr3_read_pup_reg(PUP_RL_MODE, cs, in ddr3_read_leveling_hw()
120 ddr3_read_pup_reg(PUP_RL_MODE + 0x1, in ddr3_read_leveling_hw()
731 reg = ddr3_read_pup_reg(PUP_RL_MODE + 0x1, cs, pup); in ddr3_read_leveling_single_cs_rl_mode()
1206 reg = ddr3_read_pup_reg(PUP_RL_MODE + 0x1, cs, pup); in ddr3_read_leveling_single_cs_window_mode()
Dddr3_hw_training.h327 u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup);
Dddr3_pbs.c1511 reg = (ddr3_read_pup_reg(PUP_WL_MODE, cs, pup) & 0x3FF); in ddr3_pbs_write_pup_dqs_reg()