Home
last modified time | relevance | path

Searched refs:ddr_mode (Results 1 – 15 of 15) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_init.c782 MV_DRAM_MODES *ddr_mode; in ddr3_static_training_init() local
786 ddr_mode = ddr3_get_static_ddr_mode(); in ddr3_static_training_init()
789 while (ddr_mode->vals[j].reg_addr != 0) { in ddr3_static_training_init()
791 reg_write(ddr_mode->vals[j].reg_addr, in ddr3_static_training_init()
792 ddr_mode->vals[j].reg_value); in ddr3_static_training_init()
794 if (ddr_mode->vals[j].reg_addr == in ddr3_static_training_init()
882 MV_DRAM_MODES *ddr_mode; in ddr3_static_mc_init() local
886 ddr_mode = ddr3_get_static_ddr_mode(); in ddr3_static_mc_init()
888 while (ddr_mode->regs[j].reg_addr != 0) { in ddr3_static_mc_init()
889 reg_write(ddr_mode->regs[j].reg_addr, in ddr3_static_mc_init()
[all …]
/external/u-boot/arch/arm/mach-exynos/include/mach/
Dspl.h42 enum ddr_mode mem_type; /* Type of on-board memory */
Ddmc.h431 enum ddr_mode { enum
/external/u-boot/drivers/mmc/
Dxenon_sdhci.c251 if (host->mmc->ddr_mode) { in xenon_mmc_phy_set()
343 if (host->mmc->ddr_mode) in xenon_sdhci_set_ios_post()
357 if (host->mmc->ddr_mode) in xenon_sdhci_set_ios_post()
Dsdhci-cadence.c147 if (mmc->ddr_mode) in sdhci_cdns_set_control_reg()
152 if (mmc->ddr_mode) in sdhci_cdns_set_control_reg()
Dtmio-common.c539 if (mmc->ddr_mode) in tmio_sd_set_ddr_mode()
647 mmc->clock, mmc->ddr_mode, mmc->bus_width); in tmio_sd_set_ios()
Dmmc.c188 mmc->ddr_mode = mmc_is_mode_ddr(mode); in mmc_select_mode()
257 if (mmc->ddr_mode) in mmc_set_blocklen()
2332 if (mmc->ddr_mode) { in mmc_startup()
2562 mmc->ddr_mode = 0; in mmc_start_init()
Ddw_mmc.c414 if (mmc->ddr_mode)
Dfsl_esdhc.c443 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); in esdhc_send_cmd_common()
586 int ddr_pre_div = mmc->ddr_mode ? 2 : 1; in set_sysctl()
/external/u-boot/arch/arm/mach-exynos/
Dclock_init.h40 enum ddr_mode mem_type; /* Memory type */
Ddmc_common.c75 void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode mode) in update_reset_dll()
Dclock_init_exynos5.c484 static void clock_get_mem_selection(enum ddr_mode *mem_type, in clock_get_mem_selection()
501 enum ddr_mode mem_type; in get_arm_ratios()
525 enum ddr_mode mem_type; in clock_get_mem_timings()
Dexynos5_setup.h945 void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);
/external/u-boot/include/
Dmmc.h613 int ddr_mode; member
/external/u-boot/cmd/
Dmmc.c47 mmc->ddr_mode ? " DDR" : ""); in print_mmcinfo()