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Searched refs:ddr_pll_ctrl (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/mach-omap2/am33xx/
Dclock_ti816x.c240 u32 ddr_pll_ctrl = 0; in ddr_pll_bypass_ti816x() local
243 ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); in ddr_pll_bypass_ti816x()
244 ddr_pll_ctrl &= 0xFFFFFFFB; in ddr_pll_bypass_ti816x()
245 ddr_pll_ctrl |= BIT(2); in ddr_pll_bypass_ti816x()
246 writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); in ddr_pll_bypass_ti816x()
251 u32 ddr_pll_ctrl = 0; in ddr_pll_init_ti816x() local
253 ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); in ddr_pll_init_ti816x()
254 ddr_pll_ctrl &= 0xFFFFFFF7; in ddr_pll_init_ti816x()
255 ddr_pll_ctrl |= BIT(3); in ddr_pll_init_ti816x()
256 writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); in ddr_pll_init_ti816x()
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/external/u-boot/arch/arm/mach-zynq/include/mach/
Dhardware.h39 u32 ddr_pll_ctrl; /* 0x104 */ member
/external/u-boot/drivers/clk/
Dclk_zynq.c61 return &slcr_base->ddr_pll_ctrl; in zynq_clk_get_register()