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Searched refs:ddr_sr_cntr (Results 1 – 14 of 14) sorted by relevance

/external/u-boot/board/freescale/bsc9132qds/
Dddr.c39 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
66 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
/external/u-boot/board/freescale/p1010rdb/
Dddr.c42 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
69 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
/external/u-boot/drivers/ddr/fsl/
Darm_ddr_gen3.c123 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); in fsl_ddr_set_memctl_regs()
Dmpc85xx_ddr_gen3.c146 out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); in fsl_ddr_set_memctl_regs()
Dfsl_ddr_gen4.c208 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); in fsl_ddr_set_memctl_regs()
Dinteractive.c670 CFG_REGS(ddr_sr_cntr), in print_fsl_memctl_config_regs()
761 CFG_REGS(ddr_sr_cntr), in fsl_ddr_regs_edit()
Dctrl_regs.c2304 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; in set_ddr_sr_cntr()
/external/u-boot/board/freescale/p1_twr/
Dddr.c48 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, in fixed_sdram()
/external/u-boot/board/freescale/ls1043ardb/
Dddr.h97 .ddr_sr_cntr = 0,
/external/u-boot/board/Arcturus/ucp1020/
Dddr.c108 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, in fixed_sdram()
/external/u-boot/board/freescale/bsc9131rdb/
Dddr.c40 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
/external/u-boot/include/
Dfsl_immap.h57 u32 ddr_sr_cntr; /* self refresh counter */ member
Dfsl_ddr_sdram.h287 unsigned int ddr_sr_cntr; member
/external/u-boot/board/freescale/p1_p2_rdb_pc/
Dddr.c240 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, in fixed_sdram()