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Searched refs:ddrdqclk (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-socfpga/
Dclock_manager_gen5.c224 writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK, in cm_basic_init()
225 &clock_manager_base->sdr_pll.ddrdqclk); in cm_basic_init()
280 ret = cm_write_with_phase(cfg->ddrdqclk, in cm_basic_init()
281 &clock_manager_base->sdr_pll.ddrdqclk, in cm_basic_init()
/external/u-boot/arch/arm/mach-socfpga/include/mach/
Dclock_manager_gen5.h41 u32 ddrdqclk; member
88 u32 ddrdqclk; member