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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dmips64extins.s7 dext $2, $4, 5, 10 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
8 dextu $2, $4, 34, 6 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
9 dextm $2, $4, 5, 34 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
17 dext $2, $4, 5, 10 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
18 dext $2, $4, 34, 6 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
19 dext $2, $4, 5, 34 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
24 dext $3, $4, 31, 32 # ASM: dext $3, $4, 31, 32
25 dext $3, $4, 31, 33 # ASM: dextm $3, $4, 31, 33
26 dext $3, $4, 32, 32 # ASM: dextu $3, $4, 32, 32
Dsext_64_32.ll15 ; CHECK: dext ${{[a-z0-9]+}}, ${{[a-z0-9]+}}, 0, 32
/external/swiftshader/third_party/llvm-7.0/llvm/test/Object/Mips/
Dfeature.test1 RUN: llvm-objdump -disassemble %p/../Inputs/dext-test.elf-mips64r2 | FileCheck %s
4 CHECK: dext:
6 CHECK: 4: 43 49 82 7c dext $2, $4, 5, 10
9 CHECK: c: 83 28 82 7c dext $2, $4, 2, 6
12 CHECK: 14: 43 09 82 7c dext $2, $4, 5, 2
/external/llvm/test/Object/Mips/
Dfeature.test1 RUN: llvm-objdump -disassemble %p/../Inputs/dext-test.elf-mips64r2 | FileCheck %s
4 CHECK: dext:
6 CHECK: 4: 43 49 82 7c dext $2, $4, 5, 10
9 CHECK: c: 83 28 82 7c dext $2, $4, 2, 6
12 CHECK: 14: 43 09 82 7c dext $2, $4, 5, 2
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Ddext.ll10 ; CHECK: dext $[[R0:[0-9]+]], $[[R0:[0-9]+]], 0, 32
30 ; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 32
50 ; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 20
71 ; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 5, 20
92 ; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 0, 32
103 ; CHECK: dext $[[R0:[0-9]+]], $[[R1:[0-9]+]], 8, 12
Dmips64extins.ll3 define i64 @dext(i64 %i) nounwind readnone {
5 ; CHECK-LABEL: dext:
6 ; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
Dctlz-v.ll17 ; MIPS64-DAG: dext $[[R3:[0-9]+]], $[[R2]], 0, 32
Dcttz-v.ll30 ; MIPS64-DAG: dext $[[R8:[0-9]+]], $[[R5]], 0, 32
Dload-store-left-right.ll188 ; MIPS64R2-EL-DAG: dext $[[R0]], $[[R0]], 0, 32
195 ; MIPS64R2-EB: dext $[[R0]], $[[R0]], 0, 32
529 ; MIPS64R2-EB-DAG: dext $[[R3]], $[[R3]], 0, 32
/external/llvm/test/CodeGen/Mips/
Dmips64extins.ll3 define i64 @dext(i64 %i) nounwind readnone {
5 ; CHECK-LABEL: dext:
6 ; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
/external/llvm/test/MC/Mips/
Dmips64extins.s4 dext $2, $4, 5, 10 # CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
/external/python/cpython2/Modules/zlib/
Dinftrees.c70 static const unsigned short dext[32] = { /* Distance codes 0..29 extra */ local
193 extra = dext;
/external/zlib/src/
Dinftrees.c70 static const unsigned short dext[32] = { /* Distance codes 0..29 extra */ local
193 extra = dext;
/external/zlib/src/contrib/infback9/
Dinftree9.c72 static const unsigned short dext[32] = { /* Distance codes 0..31 extra */ local
189 extra = dext;
/external/u-boot/lib/zlib/
Dinftrees.c66 static const unsigned short dext[32] = { /* Distance codes 0..29 extra */ in inflate_table() local
192 extra = dext; in inflate_table()
/external/eigen/Eigen/src/OrderingMethods/
DAmd.h98 StorageIndex d, dk, dext, lemax = 0, e, elenk, eln, i, j, k, k1, in minimum_degree_ordering() local
299 dext = w[e] - mark; /* dext = |Le\Lk| */ in minimum_degree_ordering()
300 if(dext > 0) in minimum_degree_ordering()
302 d += dext; /* sum up the set differences */ in minimum_degree_ordering()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/instverify/
Ddext-pos.mir8 name: dext
Ddext-size.mir8 name: dext
/external/zlib/src/contrib/puff/
Dpuff.c453 static const short dext[30] = { /* Extra bits for distance codes 0..29 */ in codes() local
483 dist = dists[symbol] + bits(s, dext[symbol]); in codes()
/external/llvm/test/MC/Mips/micromips64r6/
Dinvalid.s22 # FIXME: Check various 'pos + size' constraints on dext*
23 dext $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
24 dext $2, $3, 64, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
25 dext $2, $3, 1, 0 # CHECK: :[[@LINE]]:19: error: expected immediate in range 1 .. 32
26 dext $2, $3, 1, 33 # CHECK: :[[@LINE]]:19: error: expected immediate in range 1 .. 32
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/
Dsub.ll206 ; FIXME: Likewise for the sltu, dext here.
210 ; GP64-R2: dext $[[T1:[0-9]+]], $[[T0]], 0, 32
Dadd.ll179 ; GP64-R2-R6: dext $[[T4:[0-9]+]], $[[T2]], 0, 32
338 ; GP64-R2-R6: dext $[[T3:[0-9]+]], $[[T1]], 0, 32
488 ; GP64-R2-R6: dext $[[T3:[0-9]+]], $[[T1]], 0, 32
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64/
Dinvalid-mips64r2.s9 …dext $1, $2, 12, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips64/
Dinvalid-mips64r2.s9 …dext $1, $2, 12, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips64InstrInfo.td363 // For assembly parsing, we alias dextu and dextm to dext, and match by
365 // We override the generated decoder to enforce that dext always comes out
368 def DEXT : ExtBase<"dext", GPR64Opnd, uimm5_report_uimm6,
400 "dext $rt, $rs, $pos, $size", [], II_EXT, FrmR, "dext">,
959 def : MipsInstAlias<"dext $rt, $rs, $pos, $size",
962 def : MipsInstAlias<"dext $rt, $rs, $pos, $size",

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