/external/capstone/suite/MC/PowerPC/ |
D | ppc64-encoding.s.cs | 112 0x7c,0x43,0x23,0xd2 = divd 2, 3, 4 113 0x7c,0x43,0x23,0xd3 = divd. 2, 3, 4
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/external/llvm/test/MC/PowerPC/ |
D | ppc64-encoding.s | 476 # CHECK-BE: divd 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd2] 477 # CHECK-LE: divd 2, 3, 4 # encoding: [0xd2,0x23,0x43,0x7c] 478 divd 2, 3, 4 479 # CHECK-BE: divd. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd3] 480 # CHECK-LE: divd. 2, 3, 4 # encoding: [0xd3,0x23,0x43,0x7c] 481 divd. 2, 3, 4
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
D | ppc64-encoding.s | 562 # CHECK-BE: divd 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd2] 563 # CHECK-LE: divd 2, 3, 4 # encoding: [0xd2,0x23,0x43,0x7c] 564 divd 2, 3, 4 565 # CHECK-BE: divd. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd3] 566 # CHECK-LE: divd. 2, 3, 4 # encoding: [0xd3,0x23,0x43,0x7c] 567 divd. 2, 3, 4
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MSP430/ |
D | libcalls.ll | 364 define double @divd() #0 { 366 ; CHECK: divd:
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/ |
D | ppc64le-encoding.txt | 382 # CHECK: divd 2, 3, 4 385 # CHECK: divd. 2, 3, 4
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D | ppc64-encoding.txt | 406 # CHECK: divd 2, 3, 4 409 # CHECK: divd. 2, 3, 4
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/external/llvm/test/MC/Disassembler/PowerPC/ |
D | ppc64-encoding.txt | 373 # CHECK: divd 2, 3, 4 376 # CHECK: divd. 2, 3, 4
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D | ppc64le-encoding.txt | 370 # CHECK: divd 2, 3, 4 373 # CHECK: divd. 2, 3, 4
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCSchedule.td | 155 // divd IntDivD
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D | PPCInstr64Bit.td | 439 "divd $rT, $rA, $rB", IntDivD,
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/external/v8/src/compiler/ppc/ |
D | code-generator-ppc.cc | 1487 __ divd(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); in AssembleArchInstruction() local 1516 ASSEMBLE_MODULO(divd, mulld); in AssembleArchInstruction()
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/external/v8/src/ppc/ |
D | assembler-ppc.h | 1107 void divd(Register dst, Register src1, Register src2, OEBit o = LeaveOE,
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D | constants-ppc.h | 1960 V(divd, DIVD, 0x7C0003D2) \
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D | assembler-ppc.cc | 1223 void Assembler::divd(Register dst, Register src1, Register src2, OEBit o, in divd() function in v8::internal::Assembler
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/external/llvm/lib/Target/PowerPC/ |
D | PPCInstr64Bit.td | 666 "divd", "$rT, $rA, $rB", IIC_IntDivD,
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
D | PPCInstr64Bit.td | 759 "divd", "$rT, $rA, $rB", IIC_IntDivD,
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