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Searched refs:divd (Results 1 – 16 of 16) sorted by relevance

/external/capstone/suite/MC/PowerPC/
Dppc64-encoding.s.cs112 0x7c,0x43,0x23,0xd2 = divd 2, 3, 4
113 0x7c,0x43,0x23,0xd3 = divd. 2, 3, 4
/external/llvm/test/MC/PowerPC/
Dppc64-encoding.s476 # CHECK-BE: divd 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd2]
477 # CHECK-LE: divd 2, 3, 4 # encoding: [0xd2,0x23,0x43,0x7c]
478 divd 2, 3, 4
479 # CHECK-BE: divd. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd3]
480 # CHECK-LE: divd. 2, 3, 4 # encoding: [0xd3,0x23,0x43,0x7c]
481 divd. 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding.s562 # CHECK-BE: divd 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd2]
563 # CHECK-LE: divd 2, 3, 4 # encoding: [0xd2,0x23,0x43,0x7c]
564 divd 2, 3, 4
565 # CHECK-BE: divd. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd3]
566 # CHECK-LE: divd. 2, 3, 4 # encoding: [0xd3,0x23,0x43,0x7c]
567 divd. 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MSP430/
Dlibcalls.ll364 define double @divd() #0 {
366 ; CHECK: divd:
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64le-encoding.txt382 # CHECK: divd 2, 3, 4
385 # CHECK: divd. 2, 3, 4
Dppc64-encoding.txt406 # CHECK: divd 2, 3, 4
409 # CHECK: divd. 2, 3, 4
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding.txt373 # CHECK: divd 2, 3, 4
376 # CHECK: divd. 2, 3, 4
Dppc64le-encoding.txt370 # CHECK: divd 2, 3, 4
373 # CHECK: divd. 2, 3, 4
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCSchedule.td155 // divd IntDivD
DPPCInstr64Bit.td439 "divd $rT, $rA, $rB", IntDivD,
/external/v8/src/compiler/ppc/
Dcode-generator-ppc.cc1487 __ divd(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); in AssembleArchInstruction() local
1516 ASSEMBLE_MODULO(divd, mulld); in AssembleArchInstruction()
/external/v8/src/ppc/
Dassembler-ppc.h1107 void divd(Register dst, Register src1, Register src2, OEBit o = LeaveOE,
Dconstants-ppc.h1960 V(divd, DIVD, 0x7C0003D2) \
Dassembler-ppc.cc1223 void Assembler::divd(Register dst, Register src1, Register src2, OEBit o, in divd() function in v8::internal::Assembler
/external/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td666 "divd", "$rT, $rA, $rB", IIC_IntDivD,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td759 "divd", "$rT, $rA, $rB", IIC_IntDivD,