| /external/capstone/suite/MC/PowerPC/ |
| D | ppc64-encoding.s.cs | 114 0x7c,0x43,0x23,0x92 = divdu 2, 3, 4
115 0x7c,0x43,0x23,0x93 = divdu. 2, 3, 4
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| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding.s | 484 # CHECK-BE: divdu 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x92]
485 # CHECK-LE: divdu 2, 3, 4 # encoding: [0x92,0x23,0x43,0x7c]
486 divdu 2, 3, 4
487 # CHECK-BE: divdu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x93]
488 # CHECK-LE: divdu. 2, 3, 4 # encoding: [0x93,0x23,0x43,0x7c]
489 divdu. 2, 3, 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding.s | 570 # CHECK-BE: divdu 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x92]
571 # CHECK-LE: divdu 2, 3, 4 # encoding: [0x92,0x23,0x43,0x7c]
572 divdu 2, 3, 4
573 # CHECK-BE: divdu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x93]
574 # CHECK-LE: divdu. 2, 3, 4 # encoding: [0x93,0x23,0x43,0x7c]
575 divdu. 2, 3, 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64le-encoding.txt | 388 # CHECK: divdu 2, 3, 4
391 # CHECK: divdu. 2, 3, 4
|
| D | ppc64-encoding.txt | 412 # CHECK: divdu 2, 3, 4
415 # CHECK: divdu. 2, 3, 4
|
| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding.txt | 379 # CHECK: divdu 2, 3, 4
382 # CHECK: divdu. 2, 3, 4
|
| D | ppc64le-encoding.txt | 376 # CHECK: divdu 2, 3, 4
379 # CHECK: divdu. 2, 3, 4
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCSchedule.td | 156 // divdu IntDivD
|
| D | PPCInstr64Bit.td | 443 "divdu $rT, $rA, $rB", IntDivD,
|
| /external/v8/src/compiler/ppc/ |
| D | code-generator-ppc.cc | 1497 __ divdu(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); in AssembleArchInstruction() local
1532 ASSEMBLE_MODULO(divdu, mulld); in AssembleArchInstruction()
|
| /external/v8/src/ppc/ |
| D | assembler-ppc.h | 1109 void divdu(Register dst, Register src1, Register src2, OEBit o = LeaveOE,
|
| D | constants-ppc.h | 1972 V(divdu, DIVDU, 0x7C000392) \
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| D | assembler-ppc.cc | 1229 void Assembler::divdu(Register dst, Register src1, Register src2, OEBit o, in divdu() function in v8::internal::Assembler
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 669 "divdu", "$rT, $rA, $rB", IIC_IntDivD,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 762 "divdu", "$rT, $rA, $rB", IIC_IntDivD,
|