Searched refs:divm (Results 1 – 10 of 10) sorted by relevance
| /external/u-boot/arch/arm/mach-tegra/ |
| D | clock.c | 89 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, in clock_ll_read_pll() argument
102 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask; in clock_ll_read_pll()
113 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, in clock_start_pll() argument
147 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift); in clock_start_pll()
535 u32 base, divm; in clock_get_rate() local
552 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask; in clock_get_rate()
566 divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask; in clock_get_rate()
567 do_div(rate, divm); in clock_get_rate()
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| D | cpu.c | 170 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, in pllx_set_rate() argument
187 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift); in pllx_set_rate()
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| /external/u-boot/arch/arm/include/asm/arch-tegra/ |
| D | clock.h | 61 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
88 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
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| D | warmboot.h | 71 u32 divm:5; member
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| /external/u-boot/arch/arm/mach-tegra/tegra20/ |
| D | warmboot.c | 153 u32 divm, divn, divp, cpcon, lfcon; in warmboot_save_sdram_params() local
155 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp, in warmboot_save_sdram_params()
158 scratch2.pllm_base_divm = divm; in warmboot_save_sdram_params()
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| /external/llvm/test/CodeGen/X86/ |
| D | misched-copy.ll | 29 %divm = fdiv float %convm, 0.75
30 ;%addmb = fadd float %divm, %convb
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | misched-copy.ll | 29 %divm = fdiv float %convm, 0.75
30 ;%addmb = fadd float %divm, %convb
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| /external/u-boot/arch/arm/mach-tegra/tegra124/ |
| D | clock.c | 1066 u32 divm, divn, divp, cpcon; in clock_set_display_rate() local
1086 for (divm = 1; divm < max_m && best_diff; divm++) { in clock_set_display_rate()
1087 cf = ref / divm; in clock_set_display_rate()
1107 best_m = divm; in clock_set_display_rate()
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| /external/u-boot/drivers/clk/ |
| D | clk_stm32h7.c | 320 u8 divm; member
333 .divm = 4,
394 pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT; in configure_clocks()
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| D | clk_stm32mp1.c | 814 int divm, divn, divy, src; in stm32mp1_read_pll_freq() local
834 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; in stm32mp1_read_pll_freq()
838 debug(" DIVN=%d DIVM=%d DIVY=%d\n", divn, divm, divy); in stm32mp1_read_pll_freq()
859 ((unsigned long long)(divm + 1) * in stm32mp1_read_pll_freq()
862 dfout = (ulong)(refclk * (divn + 1) / (divm + 1) * (divy + 1)); in stm32mp1_read_pll_freq()
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