1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2006-2008 4 * Texas Instruments, <www.ti.com> 5 */ 6 7 #ifndef _CPU_H 8 #define _CPU_H 9 10 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 11 #include <asm/types.h> 12 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 13 14 /* Register offsets of common modules */ 15 /* Control */ 16 #ifndef __KERNEL_STRICT_NAMES 17 #ifndef __ASSEMBLY__ 18 struct ctrl { 19 u8 res1[0xC0]; 20 u16 gpmc_nadv_ale; /* 0xC0 */ 21 u16 gpmc_noe; /* 0xC2 */ 22 u16 gpmc_nwe; /* 0xC4 */ 23 u8 res2[0x22A]; 24 u32 status; /* 0x2F0 */ 25 u32 gpstatus; /* 0x2F4 */ 26 u8 res3[0x08]; 27 u32 rpubkey_0; /* 0x300 */ 28 u32 rpubkey_1; /* 0x304 */ 29 u32 rpubkey_2; /* 0x308 */ 30 u32 rpubkey_3; /* 0x30C */ 31 u32 rpubkey_4; /* 0x310 */ 32 u8 res4[0x04]; 33 u32 randkey_0; /* 0x318 */ 34 u32 randkey_1; /* 0x31C */ 35 u32 randkey_2; /* 0x320 */ 36 u32 randkey_3; /* 0x324 */ 37 u8 res5[0x124]; 38 u32 ctrl_omap_stat; /* 0x44C */ 39 }; 40 #else /* __ASSEMBLY__ */ 41 #define CONTROL_STATUS 0x2F0 42 #endif /* __ASSEMBLY__ */ 43 #endif /* __KERNEL_STRICT_NAMES */ 44 45 #ifndef __KERNEL_STRICT_NAMES 46 #ifndef __ASSEMBLY__ 47 struct ctrl_id { 48 u8 res1[0x4]; 49 u32 idcode; /* 0x04 */ 50 u32 prod_id; /* 0x08 */ 51 u32 sku_id; /* 0x0c */ 52 u8 res2[0x08]; 53 u32 die_id_0; /* 0x18 */ 54 u32 die_id_1; /* 0x1C */ 55 u32 die_id_2; /* 0x20 */ 56 u32 die_id_3; /* 0x24 */ 57 }; 58 #endif /* __ASSEMBLY__ */ 59 #endif /* __KERNEL_STRICT_NAMES */ 60 61 /* boot pin mask */ 62 #define SYSBOOT_MASK 0x1F 63 64 /* device speed */ 65 #define SKUID_CLK_MASK 0xf 66 #define SKUID_CLK_600MHZ 0x0 67 #define SKUID_CLK_720MHZ 0x8 68 69 #define GPMC_BASE (OMAP34XX_GPMC_BASE) 70 #define GPMC_CONFIG_CS0 0x60 71 #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) 72 73 #ifndef __KERNEL_STRICT_NAMES 74 #ifdef __ASSEMBLY__ 75 #define GPMC_CONFIG1 0x00 76 #define GPMC_CONFIG2 0x04 77 #define GPMC_CONFIG3 0x08 78 #define GPMC_CONFIG4 0x0C 79 #define GPMC_CONFIG5 0x10 80 #define GPMC_CONFIG6 0x14 81 #define GPMC_CONFIG7 0x18 82 #endif /* __ASSEMBLY__ */ 83 #endif /* __KERNEL_STRICT_NAMES */ 84 85 /* GPMC Mapping */ 86 #define FLASH_BASE 0x10000000 /* NOR flash, */ 87 /* aligned to 256 Meg */ 88 #define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */ 89 /* aligned to 64 Meg */ 90 #define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */ 91 /* aligned to 256 Meg */ 92 #define DEBUG_BASE 0x08000000 /* debug board */ 93 #define NAND_BASE 0x30000000 /* NAND addr */ 94 /* (actual size small port) */ 95 #define ONENAND_MAP 0x20000000 /* OneNand addr */ 96 /* (actual size small port) */ 97 /* SMS */ 98 #ifndef __KERNEL_STRICT_NAMES 99 #ifndef __ASSEMBLY__ 100 struct sms { 101 u8 res1[0x10]; 102 u32 sysconfig; /* 0x10 */ 103 u8 res2[0x34]; 104 u32 rg_att0; /* 0x48 */ 105 u8 res3[0x84]; 106 u32 class_arb0; /* 0xD0 */ 107 }; 108 #endif /* __ASSEMBLY__ */ 109 #endif /* __KERNEL_STRICT_NAMES */ 110 111 #define BURSTCOMPLETE_GROUP7 (0x1 << 31) 112 113 /* SDRC */ 114 #ifndef __KERNEL_STRICT_NAMES 115 #ifndef __ASSEMBLY__ 116 struct sdrc_cs { 117 u32 mcfg; /* 0x80 || 0xB0 */ 118 u32 mr; /* 0x84 || 0xB4 */ 119 u8 res1[0x4]; 120 u32 emr2; /* 0x8C || 0xBC */ 121 u8 res2[0x14]; 122 u32 rfr_ctrl; /* 0x84 || 0xD4 */ 123 u32 manual; /* 0xA8 || 0xD8 */ 124 u8 res3[0x4]; 125 }; 126 127 struct sdrc_actim { 128 u32 ctrla; /* 0x9C || 0xC4 */ 129 u32 ctrlb; /* 0xA0 || 0xC8 */ 130 }; 131 132 struct sdrc { 133 u8 res1[0x10]; 134 u32 sysconfig; /* 0x10 */ 135 u32 status; /* 0x14 */ 136 u8 res2[0x28]; 137 u32 cs_cfg; /* 0x40 */ 138 u32 sharing; /* 0x44 */ 139 u8 res3[0x18]; 140 u32 dlla_ctrl; /* 0x60 */ 141 u32 dlla_status; /* 0x64 */ 142 u32 dllb_ctrl; /* 0x68 */ 143 u32 dllb_status; /* 0x6C */ 144 u32 power; /* 0x70 */ 145 u8 res4[0xC]; 146 struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */ 147 }; 148 149 /* EMIF4 */ 150 typedef struct emif4 { 151 unsigned int emif_mod_id_rev; 152 unsigned int sdram_sts; 153 unsigned int sdram_config; 154 unsigned int res1; 155 unsigned int sdram_refresh_ctrl; 156 unsigned int sdram_refresh_ctrl_shdw; 157 unsigned int sdram_time1; 158 unsigned int sdram_time1_shdw; 159 unsigned int sdram_time2; 160 unsigned int sdram_time2_shdw; 161 unsigned int sdram_time3; 162 unsigned int sdram_time3_shdw; 163 unsigned char res2[8]; 164 unsigned int sdram_pwr_mgmt; 165 unsigned int sdram_pwr_mgmt_shdw; 166 unsigned char res3[32]; 167 unsigned int sdram_iodft_tlgc; 168 unsigned char res4[128]; 169 unsigned int ddr_phyctrl1; 170 unsigned int ddr_phyctrl1_shdw; 171 unsigned int ddr_phyctrl2; 172 } emif4_t; 173 174 #endif /* __ASSEMBLY__ */ 175 #endif /* __KERNEL_STRICT_NAMES */ 176 177 #define DLLPHASE_90 (0x1 << 1) 178 #define LOADDLL (0x1 << 2) 179 #define ENADLL (0x1 << 3) 180 #define DLL_DELAY_MASK 0xFF00 181 #define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8)) 182 183 #define PAGEPOLICY_HIGH (0x1 << 0) 184 #define SRFRONRESET (0x1 << 7) 185 #define PWDNEN (0x1 << 2) 186 #define WAKEUPPROC (0x1 << 26) 187 188 #define DDR_SDRAM (0x1 << 0) 189 #define DEEPPD (0x1 << 3) 190 #define B32NOT16 (0x1 << 4) 191 #define BANKALLOCATION (0x2 << 6) 192 #define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */ 193 #define ADDRMUXLEGACY (0x1 << 19) 194 #define CASWIDTH_10BITS (0x5 << 20) 195 #define RASWIDTH_13BITS (0x2 << 24) 196 #define BURSTLENGTH4 (0x2 << 0) 197 #define CASL3 (0x3 << 4) 198 #define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C) 199 #define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4) 200 #define ARE_ARCV_1 (0x1 << 0) 201 #define ARCV (0x4e2 << 8) /* Autorefresh count */ 202 #define OMAP34XX_SDRC_CS0 0x80000000 203 #define OMAP34XX_SDRC_CS1 0xA0000000 204 #define CMD_NOP 0x0 205 #define CMD_PRECHARGE 0x1 206 #define CMD_AUTOREFRESH 0x2 207 #define CMD_ENTR_PWRDOWN 0x3 208 #define CMD_EXIT_PWRDOWN 0x4 209 #define CMD_ENTR_SRFRSH 0x5 210 #define CMD_CKE_HIGH 0x6 211 #define CMD_CKE_LOW 0x7 212 #define SOFTRESET (0x1 << 1) 213 #define SMART_IDLE (0x2 << 3) 214 #define REF_ON_IDLE (0x1 << 6) 215 216 /* DMA */ 217 #ifndef __KERNEL_STRICT_NAMES 218 #ifndef __ASSEMBLY__ 219 struct dma4_chan { 220 u32 ccr; 221 u32 clnk_ctrl; 222 u32 cicr; 223 u32 csr; 224 u32 csdp; 225 u32 cen; 226 u32 cfn; 227 u32 cssa; 228 u32 cdsa; 229 u32 csel; 230 u32 csfl; 231 u32 cdel; 232 u32 cdfl; 233 u32 csac; 234 u32 cdac; 235 u32 ccen; 236 u32 ccfn; 237 u32 color; 238 }; 239 240 struct dma4 { 241 u32 revision; 242 u8 res1[0x4]; 243 u32 irqstatus_l[0x4]; 244 u32 irqenable_l[0x4]; 245 u32 sysstatus; 246 u32 ocp_sysconfig; 247 u8 res2[0x34]; 248 u32 caps_0; 249 u8 res3[0x4]; 250 u32 caps_2; 251 u32 caps_3; 252 u32 caps_4; 253 u32 gcr; 254 u8 res4[0x4]; 255 struct dma4_chan chan[32]; 256 }; 257 258 #endif /*__ASSEMBLY__ */ 259 #endif /* __KERNEL_STRICT_NAMES */ 260 261 /* timer regs offsets (32 bit regs) */ 262 263 #ifndef __KERNEL_STRICT_NAMES 264 #ifndef __ASSEMBLY__ 265 struct gptimer { 266 u32 tidr; /* 0x00 r */ 267 u8 res[0xc]; 268 u32 tiocp_cfg; /* 0x10 rw */ 269 u32 tistat; /* 0x14 r */ 270 u32 tisr; /* 0x18 rw */ 271 u32 tier; /* 0x1c rw */ 272 u32 twer; /* 0x20 rw */ 273 u32 tclr; /* 0x24 rw */ 274 u32 tcrr; /* 0x28 rw */ 275 u32 tldr; /* 0x2c rw */ 276 u32 ttgr; /* 0x30 rw */ 277 u32 twpc; /* 0x34 r*/ 278 u32 tmar; /* 0x38 rw*/ 279 u32 tcar1; /* 0x3c r */ 280 u32 tcicr; /* 0x40 rw */ 281 u32 tcar2; /* 0x44 r */ 282 }; 283 #endif /* __ASSEMBLY__ */ 284 #endif /* __KERNEL_STRICT_NAMES */ 285 286 /* enable sys_clk NO-prescale /1 */ 287 #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) 288 289 /* Watchdog */ 290 #ifndef __KERNEL_STRICT_NAMES 291 #ifndef __ASSEMBLY__ 292 struct watchdog { 293 u8 res1[0x34]; 294 u32 wwps; /* 0x34 r */ 295 u8 res2[0x10]; 296 u32 wspr; /* 0x48 rw */ 297 }; 298 #endif /* __ASSEMBLY__ */ 299 #endif /* __KERNEL_STRICT_NAMES */ 300 301 #define WD_UNLOCK1 0xAAAA 302 #define WD_UNLOCK2 0x5555 303 304 /* PRCM */ 305 #define PRCM_BASE 0x48004000 306 307 #ifndef __KERNEL_STRICT_NAMES 308 #ifndef __ASSEMBLY__ 309 struct prcm { 310 u32 fclken_iva2; /* 0x00 */ 311 u32 clken_pll_iva2; /* 0x04 */ 312 u8 res1[0x1c]; 313 u32 idlest_pll_iva2; /* 0x24 */ 314 u8 res2[0x18]; 315 u32 clksel1_pll_iva2 ; /* 0x40 */ 316 u32 clksel2_pll_iva2; /* 0x44 */ 317 u8 res3[0x8bc]; 318 u32 clken_pll_mpu; /* 0x904 */ 319 u8 res4[0x1c]; 320 u32 idlest_pll_mpu; /* 0x924 */ 321 u8 res5[0x18]; 322 u32 clksel1_pll_mpu; /* 0x940 */ 323 u32 clksel2_pll_mpu; /* 0x944 */ 324 u8 res6[0xb8]; 325 u32 fclken1_core; /* 0xa00 */ 326 u32 res_fclken2_core; 327 u32 fclken3_core; /* 0xa08 */ 328 u8 res7[0x4]; 329 u32 iclken1_core; /* 0xa10 */ 330 u32 iclken2_core; /* 0xa14 */ 331 u32 iclken3_core; /* 0xa18 */ 332 u8 res8[0x24]; 333 u32 clksel_core; /* 0xa40 */ 334 u8 res9[0xbc]; 335 u32 fclken_gfx; /* 0xb00 */ 336 u8 res10[0xc]; 337 u32 iclken_gfx; /* 0xb10 */ 338 u8 res11[0x2c]; 339 u32 clksel_gfx; /* 0xb40 */ 340 u8 res12[0xbc]; 341 u32 fclken_wkup; /* 0xc00 */ 342 u8 res13[0xc]; 343 u32 iclken_wkup; /* 0xc10 */ 344 u8 res14[0xc]; 345 u32 idlest_wkup; /* 0xc20 */ 346 u8 res15[0x1c]; 347 u32 clksel_wkup; /* 0xc40 */ 348 u8 res16[0xbc]; 349 u32 clken_pll; /* 0xd00 */ 350 u32 clken2_pll; /* 0xd04 */ 351 u8 res17[0x18]; 352 u32 idlest_ckgen; /* 0xd20 */ 353 u32 idlest2_ckgen; /* 0xd24 */ 354 u8 res18[0x18]; 355 u32 clksel1_pll; /* 0xd40 */ 356 u32 clksel2_pll; /* 0xd44 */ 357 u32 clksel3_pll; /* 0xd48 */ 358 u32 clksel4_pll; /* 0xd4c */ 359 u32 clksel5_pll; /* 0xd50 */ 360 u8 res19[0xac]; 361 u32 fclken_dss; /* 0xe00 */ 362 u8 res20[0xc]; 363 u32 iclken_dss; /* 0xe10 */ 364 u8 res21[0x2c]; 365 u32 clksel_dss; /* 0xe40 */ 366 u8 res22[0xbc]; 367 u32 fclken_cam; /* 0xf00 */ 368 u8 res23[0xc]; 369 u32 iclken_cam; /* 0xf10 */ 370 u8 res24[0x2c]; 371 u32 clksel_cam; /* 0xf40 */ 372 u8 res25[0xbc]; 373 u32 fclken_per; /* 0x1000 */ 374 u8 res26[0xc]; 375 u32 iclken_per; /* 0x1010 */ 376 u8 res27[0x2c]; 377 u32 clksel_per; /* 0x1040 */ 378 u8 res28[0xfc]; 379 u32 clksel1_emu; /* 0x1140 */ 380 u8 res29[0x2bc]; 381 u32 fclken_usbhost; /* 0x1400 */ 382 u8 res30[0xc]; 383 u32 iclken_usbhost; /* 0x1410 */ 384 }; 385 #else /* __ASSEMBLY__ */ 386 #define CM_CLKSEL_CORE 0x48004a40 387 #define CM_CLKSEL_GFX 0x48004b40 388 #define CM_CLKSEL_WKUP 0x48004c40 389 #define CM_CLKEN_PLL 0x48004d00 390 #define CM_CLKSEL1_PLL 0x48004d40 391 #define CM_CLKSEL1_EMU 0x48005140 392 #endif /* __ASSEMBLY__ */ 393 #endif /* __KERNEL_STRICT_NAMES */ 394 395 #define PRM_BASE 0x48306000 396 397 #ifndef __KERNEL_STRICT_NAMES 398 #ifndef __ASSEMBLY__ 399 struct prm { 400 u8 res1[0xd40]; 401 u32 clksel; /* 0xd40 */ 402 u8 res2[0x50c]; 403 u32 rstctrl; /* 0x1250 */ 404 u8 res3[0x1c]; 405 u32 clksrc_ctrl; /* 0x1270 */ 406 }; 407 #endif /* __ASSEMBLY__ */ 408 #endif /* __KERNEL_STRICT_NAMES */ 409 410 #define PRM_RSTCTRL 0x48307250 411 #define PRM_RSTCTRL_RESET 0x04 412 #define PRM_RSTST 0x48307258 413 #define PRM_RSTST_WARM_RESET_MASK 0x7D2 414 #define SYSCLKDIV_1 (0x1 << 6) 415 #define SYSCLKDIV_2 (0x1 << 7) 416 417 #define CLKSEL_GPT1 (0x1 << 0) 418 419 #define EN_GPT1 (0x1 << 0) 420 #define EN_32KSYNC (0x1 << 2) 421 422 #define ST_WDT2 (0x1 << 5) 423 424 #define ST_MPU_CLK (0x1 << 0) 425 426 #define ST_CORE_CLK (0x1 << 0) 427 428 #define ST_PERIPH_CLK (0x1 << 1) 429 430 #define ST_IVA2_CLK (0x1 << 0) 431 432 #define RESETDONE (0x1 << 0) 433 434 #define TCLR_ST (0x1 << 0) 435 #define TCLR_AR (0x1 << 1) 436 #define TCLR_PRE (0x1 << 5) 437 438 /* SMX-APE */ 439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) 440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) 441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) 442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) 443 444 #ifndef __KERNEL_STRICT_NAMES 445 #ifndef __ASSEMBLY__ 446 struct pm { 447 u8 res1[0x48]; 448 u32 req_info_permission_0; /* 0x48 */ 449 u8 res2[0x4]; 450 u32 read_permission_0; /* 0x50 */ 451 u8 res3[0x4]; 452 u32 wirte_permission_0; /* 0x58 */ 453 u8 res4[0x4]; 454 u32 addr_match_1; /* 0x58 */ 455 u8 res5[0x4]; 456 u32 req_info_permission_1; /* 0x68 */ 457 u8 res6[0x14]; 458 u32 addr_match_2; /* 0x80 */ 459 }; 460 #endif /*__ASSEMBLY__ */ 461 #endif /* __KERNEL_STRICT_NAMES */ 462 463 /* Permission values for registers -Full fledged permissions to all */ 464 #define UNLOCK_1 0xFFFFFFFF 465 #define UNLOCK_2 0x00000000 466 #define UNLOCK_3 0x0000FFFF 467 468 #define NOT_EARLY 0 469 470 /* I2C base */ 471 #define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) 472 #define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) 473 #define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) 474 475 /* MUSB base */ 476 #define MUSB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000) 477 478 /* OMAP3 GPIO registers */ 479 #define OMAP_GPIO_REVISION 0x0000 480 #define OMAP_GPIO_SYSCONFIG 0x0010 481 #define OMAP_GPIO_SYSSTATUS 0x0014 482 #define OMAP_GPIO_IRQSTATUS1 0x0018 483 #define OMAP_GPIO_IRQSTATUS2 0x0028 484 #define OMAP_GPIO_IRQENABLE2 0x002c 485 #define OMAP_GPIO_IRQENABLE1 0x001c 486 #define OMAP_GPIO_WAKE_EN 0x0020 487 #define OMAP_GPIO_CTRL 0x0030 488 #define OMAP_GPIO_OE 0x0034 489 #define OMAP_GPIO_DATAIN 0x0038 490 #define OMAP_GPIO_DATAOUT 0x003c 491 #define OMAP_GPIO_LEVELDETECT0 0x0040 492 #define OMAP_GPIO_LEVELDETECT1 0x0044 493 #define OMAP_GPIO_RISINGDETECT 0x0048 494 #define OMAP_GPIO_FALLINGDETECT 0x004c 495 #define OMAP_GPIO_DEBOUNCE_EN 0x0050 496 #define OMAP_GPIO_DEBOUNCE_VAL 0x0054 497 #define OMAP_GPIO_CLEARIRQENABLE1 0x0060 498 #define OMAP_GPIO_SETIRQENABLE1 0x0064 499 #define OMAP_GPIO_CLEARWKUENA 0x0080 500 #define OMAP_GPIO_SETWKUENA 0x0084 501 #define OMAP_GPIO_CLEARDATAOUT 0x0090 502 #define OMAP_GPIO_SETDATAOUT 0x0094 503 504 #endif /* _CPU_H */ 505