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Searched refs:dlr (Results 1 – 25 of 27) sorted by relevance

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/external/llvm/test/MC/SystemZ/
Dregs-bad.s51 #CHECK: dlr %r1,%r0
53 #CHECK: dlr %r3,%r0
55 #CHECK: dlr %r5,%r0
57 #CHECK: dlr %r7,%r0
59 #CHECK: dlr %r9,%r0
61 #CHECK: dlr %r11,%r0
63 #CHECK: dlr %r13,%r0
65 #CHECK: dlr %r15,%r0
67 #CHECK: dlr %f0,%r1
69 #CHECK: dlr %a0,%r1
[all …]
Dregs-good.s39 #CHECK: dlr %r0, %r0 # encoding: [0xb9,0x97,0x00,0x00]
40 #CHECK: dlr %r2, %r0 # encoding: [0xb9,0x97,0x00,0x20]
41 #CHECK: dlr %r4, %r0 # encoding: [0xb9,0x97,0x00,0x40]
42 #CHECK: dlr %r6, %r0 # encoding: [0xb9,0x97,0x00,0x60]
43 #CHECK: dlr %r8, %r0 # encoding: [0xb9,0x97,0x00,0x80]
44 #CHECK: dlr %r10, %r0 # encoding: [0xb9,0x97,0x00,0xa0]
45 #CHECK: dlr %r12, %r0 # encoding: [0xb9,0x97,0x00,0xc0]
46 #CHECK: dlr %r14, %r0 # encoding: [0xb9,0x97,0x00,0xe0]
48 dlr %r0,%r0
49 dlr %r2,%r0
[all …]
Dinsn-good.s5233 #CHECK: dlr %r0, %r0 # encoding: [0xb9,0x97,0x00,0x00]
5234 #CHECK: dlr %r0, %r15 # encoding: [0xb9,0x97,0x00,0x0f]
5235 #CHECK: dlr %r14, %r0 # encoding: [0xb9,0x97,0x00,0xe0]
5236 #CHECK: dlr %r6, %r9 # encoding: [0xb9,0x97,0x00,0x69]
5238 dlr %r0,%r0
5239 dlr %r0,%r15
5240 dlr %r14,%r0
5241 dlr %r6,%r9
Dinsn-bad.s1370 #CHECK: dlr %r1, %r0
1372 dlr %r1, %r0
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/SystemZ/
Dregs-bad.s63 #CHECK: dlr %r1,%r0
65 #CHECK: dlr %r3,%r0
67 #CHECK: dlr %r5,%r0
69 #CHECK: dlr %r7,%r0
71 #CHECK: dlr %r9,%r0
73 #CHECK: dlr %r11,%r0
75 #CHECK: dlr %r13,%r0
77 #CHECK: dlr %r15,%r0
79 #CHECK: dlr %f0,%r1
81 #CHECK: dlr %a0,%r1
[all …]
Dregs-good.s39 #CHECK: dlr %r0, %r0 # encoding: [0xb9,0x97,0x00,0x00]
40 #CHECK: dlr %r2, %r0 # encoding: [0xb9,0x97,0x00,0x20]
41 #CHECK: dlr %r4, %r0 # encoding: [0xb9,0x97,0x00,0x40]
42 #CHECK: dlr %r6, %r0 # encoding: [0xb9,0x97,0x00,0x60]
43 #CHECK: dlr %r8, %r0 # encoding: [0xb9,0x97,0x00,0x80]
44 #CHECK: dlr %r10, %r0 # encoding: [0xb9,0x97,0x00,0xa0]
45 #CHECK: dlr %r12, %r0 # encoding: [0xb9,0x97,0x00,0xc0]
46 #CHECK: dlr %r14, %r0 # encoding: [0xb9,0x97,0x00,0xe0]
48 dlr %r0,%r0
49 dlr %r2,%r0
[all …]
Dinsn-good.s7030 #CHECK: dlr %r0, %r0 # encoding: [0xb9,0x97,0x00,0x00]
7031 #CHECK: dlr %r0, %r15 # encoding: [0xb9,0x97,0x00,0x0f]
7032 #CHECK: dlr %r14, %r0 # encoding: [0xb9,0x97,0x00,0xe0]
7033 #CHECK: dlr %r6, %r9 # encoding: [0xb9,0x97,0x00,0x69]
7035 dlr %r0,%r0
7036 dlr %r0,%r15
7037 dlr %r14,%r0
7038 dlr %r6,%r9
/external/capstone/suite/MC/SystemZ/
Dregs-good.s.cs18 0xb9,0x97,0x00,0x00 = dlr %r0, %r0
19 0xb9,0x97,0x00,0x20 = dlr %r2, %r0
20 0xb9,0x97,0x00,0x40 = dlr %r4, %r0
21 0xb9,0x97,0x00,0x60 = dlr %r6, %r0
22 0xb9,0x97,0x00,0x80 = dlr %r8, %r0
23 0xb9,0x97,0x00,0xa0 = dlr %r10, %r0
24 0xb9,0x97,0x00,0xc0 = dlr %r12, %r0
25 0xb9,0x97,0x00,0xe0 = dlr %r14, %r0
Dinsn-good.s.cs668 0xb9,0x97,0x00,0x00 = dlr %r0, %r0
669 0xb9,0x97,0x00,0x0f = dlr %r0, %r15
670 0xb9,0x97,0x00,0xe0 = dlr %r14, %r0
671 0xb9,0x97,0x00,0x69 = dlr %r6, %r9
/external/llvm/test/CodeGen/SystemZ/
Dint-div-02.ll13 ; CHECK: dlr %r2, %r4
27 ; CHECK: dlr %r2, %r4
41 ; CHECK: dlr %r2, %r4
42 ; CHECK-NOT: dlr
88 ; CHECK-NOT: {{dl|dlr}}
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dint-div-02.ll13 ; CHECK: dlr %r2, %r4
27 ; CHECK: dlr %r2, %r4
41 ; CHECK: dlr %r2, %r4
42 ; CHECK-NOT: dlr
88 ; CHECK-NOT: {{dl|dlr}}
Dpr32372.ll10 ; CHECK-NEXT: dlr %r0, %r1
/external/u-boot/drivers/serial/
Dserial_uniphier.c34 u32 dlr; /* Divisor Latch Register */ member
54 writel(divisor, &port->dlr); in uniphier_serial_setbrg()
/external/llvm/test/MC/Disassembler/SystemZ/
Dinvalid-regs.txt17 # This would be "dlr %r1, %r8", but %r1 is invalid.
Dinsns.txt3049 # CHECK: dlr %r0, %r0
3052 # CHECK: dlr %r0, %r15
3055 # CHECK: dlr %r14, %r0
3058 # CHECK: dlr %r6, %r9
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/SystemZ/
Dinvalid-regs.txt17 # This would be "dlr %r1, %r8", but %r1 is invalid.
/external/u-boot/drivers/spi/
Dstm32_qspi.c27 u32 dlr; /* 0x10 */ member
293 writel(length - 1, &priv->regs->dlr); in _stm32_qspi_set_xfer_length()
406 priv->regs->ccr, priv->regs->ar, priv->regs->dlr); in _stm32_qspi_xfer()
/external/swiftshader/third_party/LLVM/test/CodeGen/SystemZ/
D08-DivRem.ll3 ; RUN: llc < %s | grep dlr | count 2
/external/u-boot/include/faraday/
Dftsdc010.h25 unsigned int dlr; /* 0x24 - data length reg */ member
/external/clang/test/SemaCXX/
Dwarn-thread-safety-analysis.cpp1551 DataLocker dlr; in bar2() local
1552 dlr.lockData(d); in bar2()
1554 dlr.unlockData(d); in bar2()
1558 DataLocker dlr; in bar3() local
1559 dlr.lockData(d1); // expected-note {{mutex acquired here}} in bar3()
1560 dlr.unlockData(d2); // \ in bar3()
1565 DataLocker dlr; in bar4() local
1566 dlr.lockData(d1); in bar4()
1570 dlr.unlockData(d1); in bar4()
/external/u-boot/drivers/mmc/
Dftsdc010_mci.c214 writel(len, &regs->dlr); in ftsdc010_request()
/external/v8/src/s390/
Dmacro-assembler-s390.cc2274 Generate_DivU32(dlr); in DivU32()
2348 Generate_ModU32(dlr); in ModU32()
Dconstants-s390.h1425 V(dlr, DLR, 0xB997) /* type = RRE DIVIDE LOGICAL (32<-64) */ \
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZInstrInfo.td905 "dlr\t{$dst, $src2}",
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.td1320 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>;

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