| /external/u-boot/arch/x86/cpu/ivybridge/ |
| D | northbridge.c | 159 dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); in sandybridge_setup_northbridge_bars()
160 dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); in sandybridge_setup_northbridge_bars()
161 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1); in sandybridge_setup_northbridge_bars()
162 dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32); in sandybridge_setup_northbridge_bars()
164 dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); in sandybridge_setup_northbridge_bars()
165 dm_pci_write_config32(dev, PCIEXBAR + 4, in sandybridge_setup_northbridge_bars()
167 dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); in sandybridge_setup_northbridge_bars()
168 dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); in sandybridge_setup_northbridge_bars()
201 dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD); in bd82x6x_northbridge_early_init()
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| D | lpc.c | 122 dm_pci_write_config32(pch, 0xb8, reg); in pch_gpi_routing()
485 dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, in bd82x6x_lpc_early_init()
487 dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1); in bd82x6x_lpc_early_init()
496 dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1); in bd82x6x_lpc_early_init()
497 dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10); in bd82x6x_lpc_early_init()
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| D | sata.c | 25 dm_pci_write_config32(dev, IDE_CONFIG, reg32); in common_sata_init()
35 dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183); in common_sata_init()
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| D | early_me.c | 90 dm_pci_write_config32(dev, ETR3, etr3); in set_global_reset()
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| /external/u-boot/arch/x86/cpu/broadwell/ |
| D | northbridge.c | 15 dm_pci_write_config32(dev, PCIEXBAR + 4, 0); in broadwell_northbridge_early_init()
17 dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1); in broadwell_northbridge_early_init()
19 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1); in broadwell_northbridge_early_init()
20 dm_pci_write_config32(dev, DMIBAR, DMI_BASE_ADDRESS | 1); in broadwell_northbridge_early_init()
21 dm_pci_write_config32(dev, EPBAR, EP_BASE_ADDRESS | 1); in broadwell_northbridge_early_init()
35 dm_pci_write_config32(dev, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN); in broadwell_northbridge_early_init()
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| D | sata.c | 66 dm_pci_write_config32(dev, 0x98, reg32); in broadwell_sata_init()
77 dm_pci_write_config32(dev, 0x94, reg32); in broadwell_sata_init()
198 dm_pci_write_config32(dev, 0x300, reg32); in broadwell_sata_init()
202 dm_pci_write_config32(dev, 0x98, reg32); in broadwell_sata_init()
207 dm_pci_write_config32(dev, 0x9c, reg32); in broadwell_sata_init()
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| D | me.c | 28 dm_pci_write_config32(dev, PCI_ME_H_GS, in intel_me_hsio_version()
52 dm_pci_write_config32(dev, PCI_ME_H_GS, in intel_me_hsio_version()
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| D | pch.c | 41 dm_pci_write_config32(dev, PCH_RCBA, RCB_BASE_ADDRESS | 1); in broadwell_pch_early_init()
43 dm_pci_write_config32(dev, PMBASE, ACPI_BASE_ADDRESS | 1); in broadwell_pch_early_init()
45 dm_pci_write_config32(dev, GPIO_BASE, GPIO_BASE_ADDRESS | 1); in broadwell_pch_early_init()
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| /external/u-boot/drivers/pci/ |
| D | pci_auto.c | 44 dm_pci_write_config32(dev, bar, 0xffffffff); in dm_pciauto_setup_device()
69 dm_pci_write_config32(dev, bar + 4, in dm_pciauto_setup_device()
104 dm_pci_write_config32(dev, bar, (u32)bar_value); in dm_pciauto_setup_device()
109 dm_pci_write_config32(dev, bar, in dm_pciauto_setup_device()
117 dm_pci_write_config32(dev, bar, 0x00000000); in dm_pciauto_setup_device()
137 dm_pci_write_config32(dev, rom_addr, 0xfffffffe); in dm_pciauto_setup_device()
146 dm_pci_write_config32(dev, rom_addr, in dm_pciauto_setup_device()
215 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, in dm_pciauto_prescan_setup_bridge()
218 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0); in dm_pciauto_prescan_setup_bridge()
285 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, in dm_pciauto_postscan_setup_bridge()
[all …]
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| D | pci_rom.c | 93 dm_pci_write_config32(dev, PCI_ROM_ADDRESS, in pci_rom_probe()
108 dm_pci_write_config32(dev, PCI_ROM_ADDRESS, rom_address); in pci_rom_probe()
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| D | pci-uclass.c | 314 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value) in dm_pci_write_config32() function
471 return dm_pci_write_config32(dev, offset, val); in dm_pci_clrset_config32()
1174 dm_pci_write_config32(dev, bar, addr); in dm_pci_write_bar32()
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| /external/u-boot/arch/x86/cpu/intel_common/ |
| D | pch.c | 14 dm_pci_write_config32(dev, SATA_SIRI, idx); in pch_common_sir_read()
22 dm_pci_write_config32(dev, SATA_SIRI, idx); in pch_common_sir_write()
23 dm_pci_write_config32(dev, SATA_SIRD, value); in pch_common_sir_write()
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| D | lpc.c | 32 dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1); in enable_port80_on_lpc()
72 dm_pci_write_config32(pch, LPC_GENX_DEC(i), reg); in lpc_common_early_init()
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| /external/u-boot/drivers/bios_emulator/ |
| D | atibios.c | 317 dm_pci_write_config32(pcidev, *bar, 0xFFFFFFFF); in PCI_findBIOSAddr()
354 dm_pci_write_config32(pcidev, reg, *base); in PCI_fixupIObase()
419 dm_pci_write_config32(pcidev, BIOSImageBAR, 0); in PCI_mapBIOSImage()
420 dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1); in PCI_mapBIOSImage()
451 dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress); in PCI_unmapBIOSImage()
452 dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_0, saveBaseAddress10); in PCI_unmapBIOSImage()
453 dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_1, saveBaseAddress14); in PCI_unmapBIOSImage()
454 dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18); in PCI_unmapBIOSImage()
455 dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20); in PCI_unmapBIOSImage()
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| D | bios.c | 301 dm_pci_write_config32(_BE_env.vgaInfo.pcidev,
320 dm_pci_write_config32(_BE_env.vgaInfo.pcidev,
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| /external/u-boot/board/intel/cougarcanyon2/ |
| D | cougarcanyon2.c | 32 dm_pci_write_config32(pch, LPC_GEN1_DEC, GEN_DEC_RANGE_256B | in board_early_init_f()
34 dm_pci_write_config32(pch, LPC_GEN2_DEC, GEN_DEC_RANGE_16B | in board_early_init_f()
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| /external/u-boot/arch/x86/cpu/queensbay/ |
| D | tnc.c | 53 dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE); in disable_igd()
54 dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE); in disable_igd()
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| /external/u-boot/cmd/ |
| D | pci.c | 122 dm_pci_write_config32(dev, reg_addr, 0xffffffff); in pci_bar_show()
124 dm_pci_write_config32(dev, reg_addr, base_low); in pci_bar_show()
138 dm_pci_write_config32(dev, reg_addr, 0xffffffff); in pci_bar_show()
140 dm_pci_write_config32(dev, reg_addr, base_high); in pci_bar_show()
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| /external/u-boot/drivers/usb/host/ |
| D | xhci-pci.c | 35 dm_pci_write_config32(dev, PCI_COMMAND, cmd); in xhci_pci_init()
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| D | ehci-pci.c | 45 dm_pci_write_config32(dev, PCI_COMMAND, cmd); in ehci_pci_init()
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| /external/u-boot/arch/x86/lib/ |
| D | bios_interrupts.c | 198 dm_pci_write_config32(dev, reg, dword); in int1a_handler()
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| /external/u-boot/arch/x86/include/asm/ |
| D | me_common.h | 370 dm_pci_write_config32(me_dev, offset, dword); in pci_write_dword_ptr()
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| /external/u-boot/arch/x86/cpu/ |
| D | irq.c | 328 dm_pci_write_config32(dev->parent, priv->actl_addr, 0); in irq_enable_sci()
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| /external/u-boot/drivers/video/ |
| D | ivybridge_igd.c | 741 dm_pci_write_config32(dev, PCI_COMMAND, reg32); in gma_func0_init()
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| /external/u-boot/drivers/spi/ |
| D | ich.c | 102 dm_pci_write_config32(dev->parent, 0xb0, 0x1000); in ich9_can_do_33mhz()
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