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Searched refs:dr0 (Results 1 – 25 of 26) sorted by relevance

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/external/linux-kselftest/tools/testing/selftests/x86/
Dmov_ss_trap.c65 unsigned long dr0, dr1, dr7; in enable_watchpoint() local
67 dr0 = (unsigned long)&ss; in enable_watchpoint()
80 if (ptrace(PTRACE_POKEUSER, parent, (void *)offsetof(struct user, u_debugreg[0]), dr0) != 0) in enable_watchpoint()
89 printf("\tDR0 = %lx, DR1 = %lx, DR7 = %lx\n", dr0, dr1, dr7); in enable_watchpoint()
/external/libffi/src/sh64/
Dsysv.S135 fld.d r15, 0, dr0
280 fst.d r31, 0, dr0
344 fst.d r14, 24, dr0
406 fld.d r14, 16, dr0
/external/python/cpython2/Modules/_ctypes/libffi/src/sh64/
Dsysv.S135 fld.d r15, 0, dr0
280 fst.d r31, 0, dr0
344 fst.d r14, 24, dr0
406 fld.d r14, 16, dr0
/external/google-breakpad/src/google_breakpad/common/
Dminidump_cpu_x86.h103 uint32_t dr0; member
Dminidump_cpu_amd64.h132 uint64_t dr0; member
/external/google-breakpad/src/client/linux/dump_writer_common/
Dthread_info.cc68 out->dr0 = dregs[0]; in FillCPUContext()
142 out->dr0 = dregs[0];
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dipra-reg-usage.ll6 …r2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4…
/external/google-breakpad/src/processor/
Ddump_context.cc281 printf(" dr0 = 0x%x\n", context_x86->dr0); in Print()
447 printf(" dr0 = 0x%" PRIx64 "\n", context_amd64->dr0); in Print()
Dsynth_minidump.cc139 D32(context.dr0); in Context()
Dminidump.cc506 Swap(&context_amd64->dr0); in Read()
796 Swap(&context_x86->dr0); in Read()
/external/google-breakpad/src/processor/testdata/
Dminidump2.dump.out92 dr0 = 0x0
143 dr0 = 0x0
639 dr0 = 0x0
/external/llvm/test/MC/X86/
Dx86-16.s293 movl %dr0,%eax
Dx86-32.s401 movl %dr0,%eax
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/X86/
Dx86-16.s305 movl %dr0,%eax
Dx86-32.s413 movl %dr0,%eax
/external/swiftshader/third_party/LLVM/test/MC/X86/
Dx86-32.s373 movl %dr0,%eax
/external/llvm/test/MC/Disassembler/X86/
Dx86-16.txt240 # CHECKX: movl %dr0, %eax
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/X86/
Dx86-16.txt240 # CHECKX: movl %dr0, %eax
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.td238 def DR0 : Register<"dr0">;
DX86GenAsmWriter.inc5433 "dr0\000dr1\000dr2\000dr3\000dr4\000dr5\000dr6\000dr7\000ds\000dx\000eax"
DX86GenAsmWriter1.inc6176 "dr0\000dr1\000dr2\000dr3\000dr4\000dr5\000dr6\000dr7\000ds\000dx\000eax"
DX86GenAsmMatcher.inc179 return 33; // "dr0"
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td266 def DR0 : X86Reg<"dr0", 0>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86RegisterInfo.td315 def DR0 : X86Reg<"dr0", 0>;
/external/mesa3d/src/mesa/x86/
Dassyntax.h129 #define DR0 dr0

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