Searched refs:dramtmg5 (Results 1 – 13 of 13) sorted by relevance
58 writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5); in mx7_dram_cfg()
35 u32 dramtmg5; member132 u32 dramtmg5; member
33 u32 dramtmg5; /* 0x0114 */ member
48 .dramtmg5 = 0x03030202,
76 u32 dramtmg5; member
51 u32 dramtmg5; /* 0x114 SDRAM Timing 5*/ member
81 DDRCTL_REG_TIMING(dramtmg5),
89 u32 dramtmg5; /* 0x6c dram timing parameters register 5 */ member
125 u32 dramtmg5; /* 0x114 */ member
185 &mctl_ctl->dramtmg5); in mctl_init()
149 writel(reg_val, &mctl_ctl->dramtmg5); in auto_set_timing_para()
181 writel(reg_val, &mctl_ctl->dramtmg5); in auto_set_timing_para()