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Searched refs:ds_add_rtn_u32 (Results 1 – 20 of 20) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Datomic_load_add.ll24 ; SI: ds_add_rtn_u32
33 ; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:20
Dlocal-atomics.ll37 ; GCN: ds_add_rtn_u32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
48 ; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
59 ; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
60 ; CIVI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
74 ; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[ONE]]
85 ; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[ONE]] offset:16
96 ; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
97 ; CIVI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
Dshl_add_ptr.ll149 ; SI: ds_add_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Datomic_load_add.ll33 ; GCN: ds_add_rtn_u32
45 ; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:20
Dlocal-atomics.ll49 ; GCN: ds_add_rtn_u32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
63 ; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
77 ; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
78 ; CIVI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
96 ; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[ONE]]
111 ; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[ONE]] offset:16
125 ; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
126 ; CIVI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
Dshl_add_ptr.ll149 ; GCN: ds_add_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
/external/llvm/test/MC/AMDGPU/
Dds.s161 ds_add_rtn_u32 v8, v2, v4 label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dds.s186 ds_add_rtn_u32 v8, v2, v4 label
Dgfx7_asm_all.s582 ds_add_rtn_u32 v5, v1, v2 offset:65535 label
585 ds_add_rtn_u32 v255, v1, v2 offset:65535 label
588 ds_add_rtn_u32 v5, v255, v2 offset:65535 label
591 ds_add_rtn_u32 v5, v1, v255 offset:65535 label
594 ds_add_rtn_u32 v5, v1, v2 label
597 ds_add_rtn_u32 v5, v1, v2 offset:0 label
600 ds_add_rtn_u32 v5, v1, v2 offset:4 label
603 ds_add_rtn_u32 v5, v1, v2 offset:65535 gds label
Dgfx8_asm_all.s522 ds_add_rtn_u32 v5, v1, v2 offset:65535 label
525 ds_add_rtn_u32 v255, v1, v2 offset:65535 label
528 ds_add_rtn_u32 v5, v255, v2 offset:65535 label
531 ds_add_rtn_u32 v5, v1, v255 offset:65535 label
534 ds_add_rtn_u32 v5, v1, v2 label
537 ds_add_rtn_u32 v5, v1, v2 offset:0 label
540 ds_add_rtn_u32 v5, v1, v2 offset:4 label
543 ds_add_rtn_u32 v5, v1, v2 offset:65535 gds label
Dgfx9_asm_all.s523 ds_add_rtn_u32 v5, v1, v2 offset:65535 label
526 ds_add_rtn_u32 v255, v1, v2 offset:65535 label
529 ds_add_rtn_u32 v5, v255, v2 offset:65535 label
532 ds_add_rtn_u32 v5, v1, v255 offset:65535 label
535 ds_add_rtn_u32 v5, v1, v2 label
538 ds_add_rtn_u32 v5, v1, v2 offset:0 label
541 ds_add_rtn_u32 v5, v1, v2 offset:4 label
544 ds_add_rtn_u32 v5, v1, v2 offset:65535 gds label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dds_vi.txt111 # VI: ds_add_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x40,0xd8,0x02,0x04,0x00,0x08]
Dgfx8_dasm_all.txt447 # CHECK: ds_add_rtn_u32 v5, v1, v2 offset:65535 ; encoding: [0xff,0xff,0x40,0xd8,0x01,0x02,0x00,…
450 # CHECK: ds_add_rtn_u32 v255, v1, v2 offset:65535 ; encoding: [0xff,0xff,0x40,0xd8,0x01,0x02,0x0…
453 # CHECK: ds_add_rtn_u32 v5, v255, v2 offset:65535 ; encoding: [0xff,0xff,0x40,0xd8,0xff,0x02,0x0…
456 # CHECK: ds_add_rtn_u32 v5, v1, v255 offset:65535 ; encoding: [0xff,0xff,0x40,0xd8,0x01,0xff,0x0…
459 # CHECK: ds_add_rtn_u32 v5, v1, v2 ; encoding: [0x00,0x00,0x40,0xd8,0x01,0x02,0x00,0x05]
462 # CHECK: ds_add_rtn_u32 v5, v1, v2 offset:4 ; encoding: [0x04,0x00,0x40,0xd8,0x01,0x02,0x00,0x05]
465 # CHECK: ds_add_rtn_u32 v5, v1, v2 offset:65535 gds ; encoding: [0xff,0xff,0x41,0xd8,0x01,0x02,0…
Dgfx9_dasm_all.txt447 # CHECK: ds_add_rtn_u32 v5, v1, v2 offset:65535 ; encoding: [0xff,0xff,0x40,0xd8,0x01,0x02,0x00,…
450 # CHECK: ds_add_rtn_u32 v255, v1, v2 offset:65535 ; encoding: [0xff,0xff,0x40,0xd8,0x01,0x02,0x0…
453 # CHECK: ds_add_rtn_u32 v5, v255, v2 offset:65535 ; encoding: [0xff,0xff,0x40,0xd8,0xff,0x02,0x0…
456 # CHECK: ds_add_rtn_u32 v5, v1, v255 offset:65535 ; encoding: [0xff,0xff,0x40,0xd8,0x01,0xff,0x0…
459 # CHECK: ds_add_rtn_u32 v5, v1, v2 ; encoding: [0x00,0x00,0x40,0xd8,0x01,0x02,0x00,0x05]
462 # CHECK: ds_add_rtn_u32 v5, v1, v2 offset:4 ; encoding: [0x04,0x00,0x40,0xd8,0x01,0x02,0x00,0x05]
465 # CHECK: ds_add_rtn_u32 v5, v1, v2 offset:65535 gds ; encoding: [0xff,0xff,0x41,0xd8,0x01,0x02,0…
/external/llvm/test/MC/Disassembler/AMDGPU/
Dds_vi.txt105 # VI: ds_add_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x40,0xd8,0x02,0x04,0x00,0x08]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DDSInstructions.td427 defm DS_ADD_RTN_U32 : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DAMDGPUAsmGFX7.rst21 …ds_add_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
DAMDGPUAsmGFX8.rst23 …ds_add_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
DAMDGPUAsmGFX9.rst23 …ds_add_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td802 defm DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VGPR_32, "ds_add_u32">;