| /external/llvm/test/MC/AMDGPU/ |
| D | ds.s | 69 ds_dec_u32 v2, v4 label
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
| D | ds.s | 86 ds_dec_u32 v2, v4 label
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| D | gfx7_asm_all.s | 87 ds_dec_u32 v1, v2 offset:65535 label
90 ds_dec_u32 v255, v2 offset:65535 label
93 ds_dec_u32 v1, v255 offset:65535 label
96 ds_dec_u32 v1, v2 label
99 ds_dec_u32 v1, v2 offset:0 label
102 ds_dec_u32 v1, v2 offset:4 label
105 ds_dec_u32 v1, v2 offset:65535 gds label
|
| D | gfx8_asm_all.s | 87 ds_dec_u32 v1, v2 offset:65535 label
90 ds_dec_u32 v255, v2 offset:65535 label
93 ds_dec_u32 v1, v255 offset:65535 label
96 ds_dec_u32 v1, v2 label
99 ds_dec_u32 v1, v2 offset:0 label
102 ds_dec_u32 v1, v2 offset:4 label
105 ds_dec_u32 v1, v2 offset:65535 gds label
|
| D | gfx9_asm_all.s | 88 ds_dec_u32 v1, v2 offset:65535 label
91 ds_dec_u32 v255, v2 offset:65535 label
94 ds_dec_u32 v1, v255 offset:65535 label
97 ds_dec_u32 v1, v2 label
100 ds_dec_u32 v1, v2 offset:0 label
103 ds_dec_u32 v1, v2 offset:4 label
106 ds_dec_u32 v1, v2 offset:65535 gds label
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.amdgcn.atomic.dec.ll | 37 ; GCN: ds_dec_u32 [[VPTR]], [[DATA]]
45 ; GCN: ds_dec_u32 v{{[0-9]+}}, [[K]] offset:16
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.amdgcn.atomic.dec.ll | 75 ; GCN: ds_dec_u32 [[VPTR]], [[DATA]]
86 ; GCN: ds_dec_u32 v{{[0-9]+}}, [[K]] offset:16
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | DSInstructions.td | 366 defm DS_DEC_U32 : DS_1A1D_NORET_mc<"ds_dec_u32">;
432 defm DS_DEC_RTN_U32 : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/ |
| D | ds_vi.txt | 36 # VI: ds_dec_u32 v2, v4 ; encoding: [0x00,0x00,0x08,0xd8,0x02,0x04,0x00,0x00]
|
| D | gfx8_dasm_all.txt | 75 # CHECK: ds_dec_u32 v1, v2 offset:65535 ; encoding: [0xff,0xff,0x08,0xd8,0x01,0x02,0x00,0x00]
78 # CHECK: ds_dec_u32 v255, v2 offset:65535 ; encoding: [0xff,0xff,0x08,0xd8,0xff,0x02,0x00,0x00]
81 # CHECK: ds_dec_u32 v1, v255 offset:65535 ; encoding: [0xff,0xff,0x08,0xd8,0x01,0xff,0x00,0x00]
84 # CHECK: ds_dec_u32 v1, v2 ; encoding: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
87 # CHECK: ds_dec_u32 v1, v2 offset:4 ; encoding: [0x04,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
90 # CHECK: ds_dec_u32 v1, v2 offset:65535 gds ; encoding: [0xff,0xff,0x09,0xd8,0x01,0x02,0x00,0x00]
|
| D | gfx9_dasm_all.txt | 75 # CHECK: ds_dec_u32 v1, v2 offset:65535 ; encoding: [0xff,0xff,0x08,0xd8,0x01,0x02,0x00,0x00]
78 # CHECK: ds_dec_u32 v255, v2 offset:65535 ; encoding: [0xff,0xff,0x08,0xd8,0xff,0x02,0x00,0x00]
81 # CHECK: ds_dec_u32 v1, v255 offset:65535 ; encoding: [0xff,0xff,0x08,0xd8,0x01,0xff,0x00,0x00]
84 # CHECK: ds_dec_u32 v1, v2 ; encoding: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
87 # CHECK: ds_dec_u32 v1, v2 offset:4 ; encoding: [0x04,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
90 # CHECK: ds_dec_u32 v1, v2 offset:65535 gds ; encoding: [0xff,0xff,0x09,0xd8,0x01,0x02,0x00,0x00]
|
| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | ds_vi.txt | 36 # VI: ds_dec_u32 v2, v4 ; encoding: [0x00,0x00,0x08,0xd8,0x02,0x04,0x00,0x00]
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 774 defm DS_DEC_U32 : DS_1A1D_NORET <0x4, "ds_dec_u32", VGPR_32>;
806 defm DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUAsmGFX7.rst | 48 …ds_dec_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
|
| D | AMDGPUAsmGFX8.rst | 52 …ds_dec_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
|
| D | AMDGPUAsmGFX9.rst | 52 …ds_dec_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
|