| /external/llvm/test/MC/AMDGPU/ |
| D | ds.s | 65 ds_inc_u32 v2, v4 label
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
| D | ds.s | 82 ds_inc_u32 v2, v4 label
|
| D | gfx7_asm_all.s | 66 ds_inc_u32 v1, v2 offset:65535 label
69 ds_inc_u32 v255, v2 offset:65535 label
72 ds_inc_u32 v1, v255 offset:65535 label
75 ds_inc_u32 v1, v2 label
78 ds_inc_u32 v1, v2 offset:0 label
81 ds_inc_u32 v1, v2 offset:4 label
84 ds_inc_u32 v1, v2 offset:65535 gds label
|
| D | gfx8_asm_all.s | 66 ds_inc_u32 v1, v2 offset:65535 label
69 ds_inc_u32 v255, v2 offset:65535 label
72 ds_inc_u32 v1, v255 offset:65535 label
75 ds_inc_u32 v1, v2 label
78 ds_inc_u32 v1, v2 offset:0 label
81 ds_inc_u32 v1, v2 offset:4 label
84 ds_inc_u32 v1, v2 offset:65535 gds label
|
| D | gfx9_asm_all.s | 67 ds_inc_u32 v1, v2 offset:65535 label
70 ds_inc_u32 v255, v2 offset:65535 label
73 ds_inc_u32 v1, v255 offset:65535 label
76 ds_inc_u32 v1, v2 label
79 ds_inc_u32 v1, v2 offset:0 label
82 ds_inc_u32 v1, v2 offset:4 label
85 ds_inc_u32 v1, v2 offset:65535 gds label
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.amdgcn.atomic.inc.ll | 37 ; GCN: ds_inc_u32 [[VPTR]], [[DATA]]
45 ; GCN: ds_inc_u32 v{{[0-9]+}}, [[K]] offset:16
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.amdgcn.atomic.inc.ll | 47 ; GCN: ds_inc_u32 [[VPTR]], [[DATA]]
58 ; GCN: ds_inc_u32 v{{[0-9]+}}, [[K]] offset:16
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | DSInstructions.td | 365 defm DS_INC_U32 : DS_1A1D_NORET_mc<"ds_inc_u32">;
431 defm DS_INC_RTN_U32 : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/ |
| D | ds_vi.txt | 33 # VI: ds_inc_u32 v2, v4 ; encoding: [0x00,0x00,0x06,0xd8,0x02,0x04,0x00,0x00]
|
| D | gfx8_dasm_all.txt | 57 # CHECK: ds_inc_u32 v1, v2 offset:65535 ; encoding: [0xff,0xff,0x06,0xd8,0x01,0x02,0x00,0x00]
60 # CHECK: ds_inc_u32 v255, v2 offset:65535 ; encoding: [0xff,0xff,0x06,0xd8,0xff,0x02,0x00,0x00]
63 # CHECK: ds_inc_u32 v1, v255 offset:65535 ; encoding: [0xff,0xff,0x06,0xd8,0x01,0xff,0x00,0x00]
66 # CHECK: ds_inc_u32 v1, v2 ; encoding: [0x00,0x00,0x06,0xd8,0x01,0x02,0x00,0x00]
69 # CHECK: ds_inc_u32 v1, v2 offset:4 ; encoding: [0x04,0x00,0x06,0xd8,0x01,0x02,0x00,0x00]
72 # CHECK: ds_inc_u32 v1, v2 offset:65535 gds ; encoding: [0xff,0xff,0x07,0xd8,0x01,0x02,0x00,0x00]
|
| D | gfx9_dasm_all.txt | 57 # CHECK: ds_inc_u32 v1, v2 offset:65535 ; encoding: [0xff,0xff,0x06,0xd8,0x01,0x02,0x00,0x00]
60 # CHECK: ds_inc_u32 v255, v2 offset:65535 ; encoding: [0xff,0xff,0x06,0xd8,0xff,0x02,0x00,0x00]
63 # CHECK: ds_inc_u32 v1, v255 offset:65535 ; encoding: [0xff,0xff,0x06,0xd8,0x01,0xff,0x00,0x00]
66 # CHECK: ds_inc_u32 v1, v2 ; encoding: [0x00,0x00,0x06,0xd8,0x01,0x02,0x00,0x00]
69 # CHECK: ds_inc_u32 v1, v2 offset:4 ; encoding: [0x04,0x00,0x06,0xd8,0x01,0x02,0x00,0x00]
72 # CHECK: ds_inc_u32 v1, v2 offset:65535 gds ; encoding: [0xff,0xff,0x07,0xd8,0x01,0x02,0x00,0x00]
|
| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | ds_vi.txt | 33 # VI: ds_inc_u32 v2, v4 ; encoding: [0x00,0x00,0x06,0xd8,0x02,0x04,0x00,0x00]
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 773 defm DS_INC_U32 : DS_1A1D_NORET <0x3, "ds_inc_u32", VGPR_32>;
805 defm DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUAsmGFX7.rst | 60 …ds_inc_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
|
| D | AMDGPUAsmGFX8.rst | 64 …ds_inc_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
|
| D | AMDGPUAsmGFX9.rst | 64 …ds_inc_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
|