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Searched refs:ds_max_rtn_i32 (Results 1 – 18 of 18) sorted by relevance

/external/llvm/test/MC/AMDGPU/
Dds.s185 ds_max_rtn_i32 v8, v2, v4 label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dds.s214 ds_max_rtn_i32 v8, v2, v4 label
Dgfx7_asm_all.s726 ds_max_rtn_i32 v5, v1, v2 offset:65535 label
729 ds_max_rtn_i32 v255, v1, v2 offset:65535 label
732 ds_max_rtn_i32 v5, v255, v2 offset:65535 label
735 ds_max_rtn_i32 v5, v1, v255 offset:65535 label
738 ds_max_rtn_i32 v5, v1, v2 label
741 ds_max_rtn_i32 v5, v1, v2 offset:0 label
744 ds_max_rtn_i32 v5, v1, v2 offset:4 label
747 ds_max_rtn_i32 v5, v1, v2 offset:65535 gds label
Dgfx8_asm_all.s666 ds_max_rtn_i32 v5, v1, v2 offset:65535 label
669 ds_max_rtn_i32 v255, v1, v2 offset:65535 label
672 ds_max_rtn_i32 v5, v255, v2 offset:65535 label
675 ds_max_rtn_i32 v5, v1, v255 offset:65535 label
678 ds_max_rtn_i32 v5, v1, v2 label
681 ds_max_rtn_i32 v5, v1, v2 offset:0 label
684 ds_max_rtn_i32 v5, v1, v2 offset:4 label
687 ds_max_rtn_i32 v5, v1, v2 offset:65535 gds label
Dgfx9_asm_all.s667 ds_max_rtn_i32 v5, v1, v2 offset:65535 label
670 ds_max_rtn_i32 v255, v1, v2 offset:65535 label
673 ds_max_rtn_i32 v5, v255, v2 offset:65535 label
676 ds_max_rtn_i32 v5, v1, v255 offset:65535 label
679 ds_max_rtn_i32 v5, v1, v2 label
682 ds_max_rtn_i32 v5, v1, v2 offset:0 label
685 ds_max_rtn_i32 v5, v1, v2 offset:4 label
688 ds_max_rtn_i32 v5, v1, v2 offset:65535 gds label
/external/llvm/test/CodeGen/AMDGPU/
Dlocal-atomics.ll246 ; GCN: ds_max_rtn_i32
256 ; GCN: ds_max_rtn_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
Dshl_add_ptr.ll243 ; SI: ds_max_rtn_i32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dlocal-atomics.ll319 ; GCN: ds_max_rtn_i32
332 ; GCN: ds_max_rtn_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
Dshl_add_ptr.ll243 ; GCN: ds_max_rtn_i32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dds_vi.txt129 # VI: ds_max_rtn_i32 v8, v2, v4 ; encoding: [0x00,0x00,0x4c,0xd8,0x02,0x04,0x00,0x08]
Dgfx8_dasm_all.txt573 # CHECK: ds_max_rtn_i32 v5, v1, v2 offset:65535 ; encoding: [0xff,0xff,0x4c,0xd8,0x01,0x02,0x00,…
576 # CHECK: ds_max_rtn_i32 v255, v1, v2 offset:65535 ; encoding: [0xff,0xff,0x4c,0xd8,0x01,0x02,0x0…
579 # CHECK: ds_max_rtn_i32 v5, v255, v2 offset:65535 ; encoding: [0xff,0xff,0x4c,0xd8,0xff,0x02,0x0…
582 # CHECK: ds_max_rtn_i32 v5, v1, v255 offset:65535 ; encoding: [0xff,0xff,0x4c,0xd8,0x01,0xff,0x0…
585 # CHECK: ds_max_rtn_i32 v5, v1, v2 ; encoding: [0x00,0x00,0x4c,0xd8,0x01,0x02,0x00,0x05]
588 # CHECK: ds_max_rtn_i32 v5, v1, v2 offset:4 ; encoding: [0x04,0x00,0x4c,0xd8,0x01,0x02,0x00,0x05]
591 # CHECK: ds_max_rtn_i32 v5, v1, v2 offset:65535 gds ; encoding: [0xff,0xff,0x4d,0xd8,0x01,0x02,0…
Dgfx9_dasm_all.txt573 # CHECK: ds_max_rtn_i32 v5, v1, v2 offset:65535 ; encoding: [0xff,0xff,0x4c,0xd8,0x01,0x02,0x00,…
576 # CHECK: ds_max_rtn_i32 v255, v1, v2 offset:65535 ; encoding: [0xff,0xff,0x4c,0xd8,0x01,0x02,0x0…
579 # CHECK: ds_max_rtn_i32 v5, v255, v2 offset:65535 ; encoding: [0xff,0xff,0x4c,0xd8,0xff,0x02,0x0…
582 # CHECK: ds_max_rtn_i32 v5, v1, v255 offset:65535 ; encoding: [0xff,0xff,0x4c,0xd8,0x01,0xff,0x0…
585 # CHECK: ds_max_rtn_i32 v5, v1, v2 ; encoding: [0x00,0x00,0x4c,0xd8,0x01,0x02,0x00,0x05]
588 # CHECK: ds_max_rtn_i32 v5, v1, v2 offset:4 ; encoding: [0x04,0x00,0x4c,0xd8,0x01,0x02,0x00,0x05]
591 # CHECK: ds_max_rtn_i32 v5, v1, v2 offset:65535 gds ; encoding: [0xff,0xff,0x4d,0xd8,0x01,0x02,0…
/external/llvm/test/MC/Disassembler/AMDGPU/
Dds_vi.txt123 # VI: ds_max_rtn_i32 v8, v2, v4 ; encoding: [0x00,0x00,0x4c,0xd8,0x02,0x04,0x00,0x08]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DDSInstructions.td434 defm DS_MAX_RTN_I32 : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DAMDGPUAsmGFX7.rst68 …ds_max_rtn_i32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
DAMDGPUAsmGFX8.rst72 …ds_max_rtn_i32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
DAMDGPUAsmGFX9.rst72 …ds_max_rtn_i32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td808 defm DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "ds_max_rtn_i32", VGPR_32, "ds_max_i32">;