| /external/llvm/test/MC/AMDGPU/ |
| D | ds.s | 169 ds_rsub_rtn_u32 v8, v2, v4 label
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
| D | ds.s | 198 ds_rsub_rtn_u32 v8, v2, v4 label
|
| D | gfx7_asm_all.s | 630 ds_rsub_rtn_u32 v5, v1, v2 offset:65535 label
633 ds_rsub_rtn_u32 v255, v1, v2 offset:65535 label
636 ds_rsub_rtn_u32 v5, v255, v2 offset:65535 label
639 ds_rsub_rtn_u32 v5, v1, v255 offset:65535 label
642 ds_rsub_rtn_u32 v5, v1, v2 label
645 ds_rsub_rtn_u32 v5, v1, v2 offset:0 label
648 ds_rsub_rtn_u32 v5, v1, v2 offset:4 label
651 ds_rsub_rtn_u32 v5, v1, v2 offset:65535 gds label
|
| D | gfx8_asm_all.s | 570 ds_rsub_rtn_u32 v5, v1, v2 offset:65535 label
573 ds_rsub_rtn_u32 v255, v1, v2 offset:65535 label
576 ds_rsub_rtn_u32 v5, v255, v2 offset:65535 label
579 ds_rsub_rtn_u32 v5, v1, v255 offset:65535 label
582 ds_rsub_rtn_u32 v5, v1, v2 label
585 ds_rsub_rtn_u32 v5, v1, v2 offset:0 label
588 ds_rsub_rtn_u32 v5, v1, v2 offset:4 label
591 ds_rsub_rtn_u32 v5, v1, v2 offset:65535 gds label
|
| D | gfx9_asm_all.s | 571 ds_rsub_rtn_u32 v5, v1, v2 offset:65535 label
574 ds_rsub_rtn_u32 v255, v1, v2 offset:65535 label
577 ds_rsub_rtn_u32 v5, v255, v2 offset:65535 label
580 ds_rsub_rtn_u32 v5, v1, v255 offset:65535 label
583 ds_rsub_rtn_u32 v5, v1, v2 label
586 ds_rsub_rtn_u32 v5, v1, v2 offset:0 label
589 ds_rsub_rtn_u32 v5, v1, v2 offset:4 label
592 ds_rsub_rtn_u32 v5, v1, v2 offset:65535 gds label
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/ |
| D | ds_vi.txt | 117 # VI: ds_rsub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x44,0xd8,0x02,0x04,0x00,0x08]
|
| D | gfx8_dasm_all.txt | 489 # CHECK: ds_rsub_rtn_u32 v5, v1, v2 offset:65535 ; encoding: [0xff,0xff,0x44,0xd8,0x01,0x02,0x00…
492 # CHECK: ds_rsub_rtn_u32 v255, v1, v2 offset:65535 ; encoding: [0xff,0xff,0x44,0xd8,0x01,0x02,0x…
495 # CHECK: ds_rsub_rtn_u32 v5, v255, v2 offset:65535 ; encoding: [0xff,0xff,0x44,0xd8,0xff,0x02,0x…
498 # CHECK: ds_rsub_rtn_u32 v5, v1, v255 offset:65535 ; encoding: [0xff,0xff,0x44,0xd8,0x01,0xff,0x…
501 # CHECK: ds_rsub_rtn_u32 v5, v1, v2 ; encoding: [0x00,0x00,0x44,0xd8,0x01,0x02,0x00,0x05]
504 # CHECK: ds_rsub_rtn_u32 v5, v1, v2 offset:4 ; encoding: [0x04,0x00,0x44,0xd8,0x01,0x02,0x00,0x0…
507 # CHECK: ds_rsub_rtn_u32 v5, v1, v2 offset:65535 gds ; encoding: [0xff,0xff,0x45,0xd8,0x01,0x02,…
|
| D | gfx9_dasm_all.txt | 489 # CHECK: ds_rsub_rtn_u32 v5, v1, v2 offset:65535 ; encoding: [0xff,0xff,0x44,0xd8,0x01,0x02,0x00…
492 # CHECK: ds_rsub_rtn_u32 v255, v1, v2 offset:65535 ; encoding: [0xff,0xff,0x44,0xd8,0x01,0x02,0x…
495 # CHECK: ds_rsub_rtn_u32 v5, v255, v2 offset:65535 ; encoding: [0xff,0xff,0x44,0xd8,0xff,0x02,0x…
498 # CHECK: ds_rsub_rtn_u32 v5, v1, v255 offset:65535 ; encoding: [0xff,0xff,0x44,0xd8,0x01,0xff,0x…
501 # CHECK: ds_rsub_rtn_u32 v5, v1, v2 ; encoding: [0x00,0x00,0x44,0xd8,0x01,0x02,0x00,0x05]
504 # CHECK: ds_rsub_rtn_u32 v5, v1, v2 offset:4 ; encoding: [0x04,0x00,0x44,0xd8,0x01,0x02,0x00,0x0…
507 # CHECK: ds_rsub_rtn_u32 v5, v1, v2 offset:65535 gds ; encoding: [0xff,0xff,0x45,0xd8,0x01,0x02,…
|
| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | ds_vi.txt | 111 # VI: ds_rsub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x44,0xd8,0x02,0x04,0x00,0x08]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | DSInstructions.td | 430 defm DS_RSUB_RTN_U32 : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUAsmGFX7.rst | 122 …ds_rsub_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
|
| D | AMDGPUAsmGFX8.rst | 127 …ds_rsub_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
|
| D | AMDGPUAsmGFX9.rst | 133 …ds_rsub_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 804 defm DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
|