/external/llvm/test/CodeGen/AMDGPU/ |
D | atomic_load_sub.ll | 7 ; SI: ds_sub_u32 15 ; SI: ds_sub_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
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D | local-atomics.ll | 391 ; GCN: ds_sub_u32 399 ; GCN: ds_sub_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 409 ; GCN: ds_sub_u32 v{{[0-9]+}}, [[ONE]] 418 ; GCN: ds_sub_u32 v{{[0-9]+}}, [[ONE]] offset:16
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
D | atomic_load_sub.ll | 11 ; GCN: ds_sub_u32 22 ; GCN: ds_sub_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
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D | local-atomics.ll | 506 ; GCN: ds_sub_u32 517 ; GCN: ds_sub_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 530 ; GCN: ds_sub_u32 v{{[0-9]+}}, [[ONE]] 542 ; GCN: ds_sub_u32 v{{[0-9]+}}, [[ONE]] offset:16
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/external/llvm/test/MC/AMDGPU/ |
D | ds.s | 57 ds_sub_u32 v2, v4 label
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
D | ds.s | 74 ds_sub_u32 v2, v4 label
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D | gfx7_asm_all.s | 24 ds_sub_u32 v1, v2 offset:65535 label 27 ds_sub_u32 v255, v2 offset:65535 label 30 ds_sub_u32 v1, v255 offset:65535 label 33 ds_sub_u32 v1, v2 label 36 ds_sub_u32 v1, v2 offset:0 label 39 ds_sub_u32 v1, v2 offset:4 label 42 ds_sub_u32 v1, v2 offset:65535 gds label
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D | gfx8_asm_all.s | 24 ds_sub_u32 v1, v2 offset:65535 label 27 ds_sub_u32 v255, v2 offset:65535 label 30 ds_sub_u32 v1, v255 offset:65535 label 33 ds_sub_u32 v1, v2 label 36 ds_sub_u32 v1, v2 offset:0 label 39 ds_sub_u32 v1, v2 offset:4 label 42 ds_sub_u32 v1, v2 offset:65535 gds label
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D | gfx9_asm_all.s | 25 ds_sub_u32 v1, v2 offset:65535 label 28 ds_sub_u32 v255, v2 offset:65535 label 31 ds_sub_u32 v1, v255 offset:65535 label 34 ds_sub_u32 v1, v2 label 37 ds_sub_u32 v1, v2 offset:0 label 40 ds_sub_u32 v1, v2 offset:4 label 43 ds_sub_u32 v1, v2 offset:65535 gds label
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
D | DSInstructions.td | 363 defm DS_SUB_U32 : DS_1A1D_NORET_mc<"ds_sub_u32">; 429 defm DS_SUB_RTN_U32 : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/ |
D | ds_vi.txt | 27 # VI: ds_sub_u32 v2, v4 ; encoding: [0x00,0x00,0x02,0xd8,0x02,0x04,0x00,0x00]
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D | gfx8_dasm_all.txt | 21 # CHECK: ds_sub_u32 v1, v2 offset:65535 ; encoding: [0xff,0xff,0x02,0xd8,0x01,0x02,0x00,0x00] 24 # CHECK: ds_sub_u32 v255, v2 offset:65535 ; encoding: [0xff,0xff,0x02,0xd8,0xff,0x02,0x00,0x00] 27 # CHECK: ds_sub_u32 v1, v255 offset:65535 ; encoding: [0xff,0xff,0x02,0xd8,0x01,0xff,0x00,0x00] 30 # CHECK: ds_sub_u32 v1, v2 ; encoding: [0x00,0x00,0x02,0xd8,0x01,0x02,0x00,0x00] 33 # CHECK: ds_sub_u32 v1, v2 offset:4 ; encoding: [0x04,0x00,0x02,0xd8,0x01,0x02,0x00,0x00] 36 # CHECK: ds_sub_u32 v1, v2 offset:65535 gds ; encoding: [0xff,0xff,0x03,0xd8,0x01,0x02,0x00,0x00]
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D | gfx9_dasm_all.txt | 21 # CHECK: ds_sub_u32 v1, v2 offset:65535 ; encoding: [0xff,0xff,0x02,0xd8,0x01,0x02,0x00,0x00] 24 # CHECK: ds_sub_u32 v255, v2 offset:65535 ; encoding: [0xff,0xff,0x02,0xd8,0xff,0x02,0x00,0x00] 27 # CHECK: ds_sub_u32 v1, v255 offset:65535 ; encoding: [0xff,0xff,0x02,0xd8,0x01,0xff,0x00,0x00] 30 # CHECK: ds_sub_u32 v1, v2 ; encoding: [0x00,0x00,0x02,0xd8,0x01,0x02,0x00,0x00] 33 # CHECK: ds_sub_u32 v1, v2 offset:4 ; encoding: [0x04,0x00,0x02,0xd8,0x01,0x02,0x00,0x00] 36 # CHECK: ds_sub_u32 v1, v2 offset:65535 gds ; encoding: [0xff,0xff,0x03,0xd8,0x01,0x02,0x00,0x00]
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/external/llvm/test/MC/Disassembler/AMDGPU/ |
D | ds_vi.txt | 27 # VI: ds_sub_u32 v2, v4 ; encoding: [0x00,0x00,0x02,0xd8,0x02,0x04,0x00,0x00]
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/external/llvm/lib/Target/AMDGPU/ |
D | SIInstructions.td | 771 defm DS_SUB_U32 : DS_1A1D_NORET <0x1, "ds_sub_u32", VGPR_32>; 803 defm DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
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/external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
D | AMDGPUAsmGFX7.rst | 132 …ds_sub_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
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D | AMDGPUAsmGFX8.rst | 137 …ds_sub_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
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D | AMDGPUAsmGFX9.rst | 143 …ds_sub_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_of…
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