/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
D | ds-err.s | 29 ds_swizzle_b32 v8, v2 offset label 32 ds_swizzle_b32 v8, v2 offset: label 35 ds_swizzle_b32 v8, v2 offset- label 38 ds_swizzle_b32 v8, v2 offset:SWIZZLE(QUAD_PERM, 0, 1, 2, 3) label 41 ds_swizzle_b32 v8, v2 offset:swizzle(quad_perm, 0, 1, 2, 3) label 44 ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1) label 47 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM label 50 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2) label 53 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3 label 56 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3, 4) label [all …]
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D | ds.s | 518 ds_swizzle_b32 v8, v2 label 522 ds_swizzle_b32 v8, v2 gds label 526 ds_swizzle_b32 v8, v2 offset:0xFFFF label 530 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3) label 534 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 2, 1, 3, 3) label 538 ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,1) label 542 ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,2) label 546 ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,4) label 550 ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,8) label 554 ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,16) label [all …]
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D | gfx7_asm_all.s | 1122 ds_swizzle_b32 v5, v1 offset:65535 label 1125 ds_swizzle_b32 v255, v1 offset:65535 label 1128 ds_swizzle_b32 v5, v255 offset:65535 label 1131 ds_swizzle_b32 v5, v1 label 1134 ds_swizzle_b32 v5, v1 offset:0 label 1137 ds_swizzle_b32 v5, v1 offset:4 label 1140 ds_swizzle_b32 v5, v1 offset:65535 gds label
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D | gfx8_asm_all.s | 1251 ds_swizzle_b32 v5, v1 offset:65535 label 1254 ds_swizzle_b32 v255, v1 offset:65535 label 1257 ds_swizzle_b32 v5, v255 offset:65535 label 1260 ds_swizzle_b32 v5, v1 label 1263 ds_swizzle_b32 v5, v1 offset:0 label 1266 ds_swizzle_b32 v5, v1 offset:4 label 1269 ds_swizzle_b32 v5, v1 offset:65535 gds label
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D | gfx9_asm_all.s | 1252 ds_swizzle_b32 v5, v1 offset:65535 label 1255 ds_swizzle_b32 v255, v1 offset:65535 label 1258 ds_swizzle_b32 v5, v255 offset:65535 label 1261 ds_swizzle_b32 v5, v1 label 1264 ds_swizzle_b32 v5, v1 offset:0 label 1267 ds_swizzle_b32 v5, v1 offset:4 label 1270 ds_swizzle_b32 v5, v1 offset:65535 gds label
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/external/llvm/test/CodeGen/AMDGPU/ |
D | llvm.amdgcn.ds.swizzle.ll | 7 ; CHECK: ds_swizzle_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:100
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
D | llvm.amdgcn.ds.swizzle.ll | 7 ; CHECK: ds_swizzle_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:swizzle(BITMASK_PERM,"00p11")
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/external/llvm/test/MC/AMDGPU/ |
D | ds.s | 241 ds_swizzle_b32 v8, v2 label
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/ |
D | ds_vi.txt | 171 # VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08] 174 # VI: ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0x7b,0xd8,0x02,0x00,0x00,0x08]
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D | gfx8_dasm_all.txt | 1077 # CHECK: ds_swizzle_b32 v5, v1 ; encoding: [0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
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D | gfx9_dasm_all.txt | 1077 # CHECK: ds_swizzle_b32 v5, v1 ; encoding: [0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
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/external/llvm/test/MC/Disassembler/AMDGPU/ |
D | ds_vi.txt | 165 # VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
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/external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
D | AMDGPUOperandSyntax.rst | 72 This is a special modifier which may be used with *ds_swizzle_b32* instruction only.
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D | AMDGPUAsmGFX7.rst | 134 …ds_swizzle_b32 dst, src0 :ref:`sw_offset16<amdgpu_synid_sw_of…
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D | AMDGPUAsmGFX8.rst | 139 …ds_swizzle_b32 dst, src0 :ref:`sw_offset16<amdgpu_synid_sw_of…
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D | AMDGPUAsmGFX9.rst | 145 …ds_swizzle_b32 dst, src0 :ref:`sw_offset16<amdgpu_synid_sw_of…
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
D | DSInstructions.td | 512 def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>;
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/external/llvm/lib/Target/AMDGPU/ |
D | SIInstructions.td | 828 defm DS_SWIZZLE_B32 : DS_1A_RET_ <dsop<0x35, 0x3d>, "ds_swizzle_b32", VGPR_32>;
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