Searched refs:dshd (Results 1 – 25 of 41) sorted by relevance
12
/external/llvm/test/MC/Mips/mips32r3/ |
D | invalid-mips64r2.s | 9 …dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not curr…
|
/external/llvm/test/MC/Mips/mips32r5/ |
D | invalid-mips64r2.s | 9 …dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not curr…
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r2/ |
D | invalid-mips64r2.s | 9 …dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not curr…
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r3/ |
D | invalid-mips64r2.s | 9 …dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not curr…
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r5/ |
D | invalid-mips64r2.s | 9 …dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not curr…
|
/external/llvm/test/MC/Mips/mips32r2/ |
D | invalid-mips64r2.s | 9 …dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not curr…
|
/external/llvm/test/MC/Mips/mips4/ |
D | invalid-mips64r2.s | 15 …dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64/ |
D | invalid-mips64r2.s | 21 …dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
/external/llvm/test/MC/Mips/mips64/ |
D | invalid-mips64r2.s | 21 …dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips4/ |
D | invalid-mips64r2.s | 15 …dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips5/ |
D | invalid-mips64r2.s | 20 …dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
/external/llvm/test/MC/Mips/mips5/ |
D | invalid-mips64r2.s | 20 …dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
/external/llvm/test/CodeGen/Mips/ |
D | bswap.ll | 42 ; MIPS64: dshd ${{[0-9]+}}, $[[R0]]
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
D | bswap.ll | 53 ; MIPS64: dshd ${{[0-9]+}}, $[[R0]]
|
/external/llvm/lib/Target/Mips/ |
D | MicroMips64r6InstrInfo.td | 51 class DSHD_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dshd", 0b1111101100>; 222 class DSHD_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dshd", GPR64Opnd>;
|
/external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
D | valid-mips64r2-el.txt | 117 0x64 0x11 0x1d 0x7c # CHECK: dshd $2, $sp 271 0x64 0x19 0x0e 0x7c # CHECK: dshd $3, $14
|
D | valid-mips64r2.txt | 419 0x7c 0x0e 0x19 0x64 # CHECK: dshd $3, $14 421 0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r2/ |
D | valid-mips64r2-el.txt | 118 0x64 0x11 0x1d 0x7c # CHECK: dshd $2, $sp 276 0x64 0x19 0x0e 0x7c # CHECK: dshd $3, $14
|
D | valid-mips64r2.txt | 424 0x7c 0x0e 0x19 0x64 # CHECK: dshd $3, $14 426 0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp
|
/external/llvm/test/MC/Mips/micromips64r6/ |
D | valid.s | 273 dshd $3, $4 # CHECK: dshd $3, $4 # encoding: [0x58,0x64,0xfb,0x3c]
|
/external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
D | valid-mips64r5.txt | 417 0x7c 0x0e 0x19 0x64 # CHECK: dshd $3, $14 419 0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r5/ |
D | valid-mips64r5.txt | 422 0x7c 0x0e 0x19 0x64 # CHECK: dshd $3, $14 424 0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r3/ |
D | valid-mips64r3.txt | 422 0x7c 0x0e 0x19 0x64 # CHECK: dshd $3, $14 424 0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp
|
/external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
D | valid-mips64r3.txt | 417 0x7c 0x0e 0x19 0x64 # CHECK: dshd $3, $14 419 0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp
|
/external/llvm/test/MC/Mips/mips64r2/ |
D | valid.s | 102 dshd $v0,$sp
|
12