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Searched refs:dshd (Results 1 – 25 of 41) sorted by relevance

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/external/llvm/test/MC/Mips/mips32r3/
Dinvalid-mips64r2.s9dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not curr…
/external/llvm/test/MC/Mips/mips32r5/
Dinvalid-mips64r2.s9dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not curr…
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r2/
Dinvalid-mips64r2.s9dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not curr…
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r3/
Dinvalid-mips64r2.s9dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not curr…
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r5/
Dinvalid-mips64r2.s9dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not curr…
/external/llvm/test/MC/Mips/mips32r2/
Dinvalid-mips64r2.s9dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not curr…
/external/llvm/test/MC/Mips/mips4/
Dinvalid-mips64r2.s15dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64/
Dinvalid-mips64r2.s21dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips64/
Dinvalid-mips64r2.s21dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips4/
Dinvalid-mips64r2.s15dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips5/
Dinvalid-mips64r2.s20dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips5/
Dinvalid-mips64r2.s20dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/CodeGen/Mips/
Dbswap.ll42 ; MIPS64: dshd ${{[0-9]+}}, $[[R0]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dbswap.ll53 ; MIPS64: dshd ${{[0-9]+}}, $[[R0]]
/external/llvm/lib/Target/Mips/
DMicroMips64r6InstrInfo.td51 class DSHD_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dshd", 0b1111101100>;
222 class DSHD_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dshd", GPR64Opnd>;
/external/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-mips64r2-el.txt117 0x64 0x11 0x1d 0x7c # CHECK: dshd $2, $sp
271 0x64 0x19 0x0e 0x7c # CHECK: dshd $3, $14
Dvalid-mips64r2.txt419 0x7c 0x0e 0x19 0x64 # CHECK: dshd $3, $14
421 0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-mips64r2-el.txt118 0x64 0x11 0x1d 0x7c # CHECK: dshd $2, $sp
276 0x64 0x19 0x0e 0x7c # CHECK: dshd $3, $14
Dvalid-mips64r2.txt424 0x7c 0x0e 0x19 0x64 # CHECK: dshd $3, $14
426 0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp
/external/llvm/test/MC/Mips/micromips64r6/
Dvalid.s273 dshd $3, $4 # CHECK: dshd $3, $4 # encoding: [0x58,0x64,0xfb,0x3c]
/external/llvm/test/MC/Disassembler/Mips/mips64r5/
Dvalid-mips64r5.txt417 0x7c 0x0e 0x19 0x64 # CHECK: dshd $3, $14
419 0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r5/
Dvalid-mips64r5.txt422 0x7c 0x0e 0x19 0x64 # CHECK: dshd $3, $14
424 0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r3/
Dvalid-mips64r3.txt422 0x7c 0x0e 0x19 0x64 # CHECK: dshd $3, $14
424 0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp
/external/llvm/test/MC/Disassembler/Mips/mips64r3/
Dvalid-mips64r3.txt417 0x7c 0x0e 0x19 0x64 # CHECK: dshd $3, $14
419 0x7c 0x1d 0x11 0x64 # CHECK: dshd $2, $sp
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s102 dshd $v0,$sp

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