Searched refs:dst_regs (Results 1 – 8 of 8) sorted by relevance
| /external/mesa3d/src/intel/compiler/ |
| D | brw_eu_validate.c | 809 unsigned dst_regs = registers_read(dst_access_mask); in region_alignment_rules() local
828 if (dst_regs == 1 && (src0_regs == 2 || src1_regs == 2)) { in region_alignment_rules()
880 if (dst_regs == 2) { in region_alignment_rules()
927 if (devinfo->gen <= 7 && dst_regs == 2) { in region_alignment_rules()
992 if (devinfo->gen <= 7 && dst_regs == 2) { in region_alignment_rules()
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrFormats.td | 262 bits<3> dst_regs;
269 let Inst{9-7} = dst_regs;
|
| D | MicroMipsInstrInfo.td | 230 MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
231 !strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrFormats.td | 275 bits<3> dst_regs;
282 let Inst{9-7} = dst_regs;
|
| D | MicroMips32r6InstrFormats.td | 734 bits<3> dst_regs;
741 let Inst{9-7} = dst_regs;
|
| D | MicroMipsInstrInfo.td | 250 MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
251 !strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
|
| /external/v8/src/wasm/baseline/ |
| D | liftoff-compiler.cc | 606 LiftoffRegister dst_regs[] = {ret_reg, dst}; in EmitTypeConversion() local
607 GenerateCCall(dst_regs, &sig, dst_type, &src, ext_ref); in EmitTypeConversion()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCCodeEmitter.inc | 2966 // op: dst_regs
2979 // op: dst_regs
|