| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| D | sb_bc_builder.cpp | 428 .DST_REL(bc.dst_rel) in build_alu()
446 .DST_REL(bc.dst_rel) in build_alu()
460 .DST_REL(bc.dst_rel) in build_alu()
475 .DST_REL(bc.dst_rel) in build_alu()
491 .DST_REL(bc.dst_rel) in build_alu()
542 .DST_REL(bc.dst_rel) in build_fetch_tex()
585 .DST_REL_MODE(bc.dst_rel) in build_fetch_gds()
650 .DST_REL(bc.dst_rel) in build_fetch_vtx()
|
| D | sb_bc_decoder.cpp | 353 bc.dst_rel = w1.get_DST_REL(); in decode_alu()
370 bc.dst_rel = w1.get_DST_REL(); in decode_alu()
389 bc.dst_rel = w1.get_DST_REL(); in decode_alu()
474 bc.dst_rel = w1.get_DST_REL(); in decode_fetch()
589 bc.dst_rel = w1.get_DST_REL(); in decode_fetch_vtx()
|
| D | sb_bc_parser.cpp | 296 if (n->bc.dst_rel) in decode_alu_group()
454 assert(!n->bc.dst_rel || n->bc.index_mode == INDEX_AR_X); in prepare_alu_group()
457 n->bc.dst_rel); in prepare_alu_group()
494 prev_alu->bc.dst_rel); in prepare_alu_group()
630 if (n->bc.src_rel || n->bc.dst_rel) in decode_fetch_clause()
|
| D | sb_bc_dump.cpp | 237 print_sel(s, sel, alu.dst_rel, alu.index_mode, 0); in print_dst()
464 print_sel(s, n.bc.dst_gpr, n.bc.dst_rel, INDEX_LOOP, 0); in dump()
|
| D | sb_bc_finalize.cpp | 330 n->bc.dst_rel = 1; in finalize_alu_group()
333 n->bc.dst_rel = 0; in finalize_alu_group()
472 if (pn->bc.dst_rel) { in finalize_alu_src()
|
| D | sb_bc.h | 508 unsigned dst_rel:1; member
548 unsigned dst_rel:1; member
|
| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_asm.h | 75 unsigned dst_rel; member
131 unsigned dst_rel; member
|
| D | eg_asm.c | 242 S_SQ_MEM_GDS_WORD1_DST_REL(gds->dst_rel) | in eg_bytecode_gds_build()
|
| D | r600_asm.c | 1556 S_SQ_TEX_WORD1_DST_REL(tex->dst_rel) | in r600_bytecode_tex_build()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 108 bits<1> dst_rel;
116 let Word1{28} = dst_rel;
|
| D | R600Instructions.td | 96 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
101 "$clamp $last $dst$write$dst_rel$omod, "
138 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
144 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
178 (ins REL:$dst_rel, CLAMP:$clamp,
184 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, "
|
| D | R600InstrInfo.cpp | 1161 setImmOperand(*Mov, AMDGPU::OpName::dst_rel, 1); in buildIndirectWrite()
1319 OPERAND_CASE(AMDGPU::OpName::dst_rel) in getSlotedOps()
1360 AMDGPU::OpName::dst_rel, in buildSlotOfVectorInstruction()
|
| D | EvergreenInstructions.td | 402 let dst_rel = 0;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | R600InstrFormats.td | 118 bits<1> dst_rel;
126 let Word1{28} = dst_rel;
|
| D | R600Instructions.td | 107 (ins WRITE:$write, OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
112 "$clamp $last $dst$write$dst_rel$omod, "
149 OMOD:$omod, REL:$dst_rel, CLAMP:$clamp,
155 "$clamp $last $update_exec_mask$update_pred$dst$write$dst_rel$omod, "
189 (ins REL:$dst_rel, CLAMP:$clamp,
195 !strconcat(" ", opName, "$clamp $last $dst$dst_rel, "
|
| D | R600InstrInfo.cpp | 1142 setImmOperand(*Mov, R600::OpName::dst_rel, 1); in buildIndirectWrite()
1298 OPERAND_CASE(R600::OpName::dst_rel) in getSlotedOps()
1339 R600::OpName::dst_rel, in buildSlotOfVectorInstruction()
|
| D | EvergreenInstructions.td | 476 let dst_rel = 0;
|
| /external/mesa3d/src/gallium/drivers/freedreno/ir3/ |
| D | instr-a3xx.h | 353 uint32_t dst_rel : 1; member
|
| D | disasm-a3xx.c | 201 cat1->dst_rel); in print_instr_cat1()
|
| D | ir3.c | 184 cat1->dst_rel = !!(dst->flags & IR3_REG_RELATIV); in emit_cat1()
|
| /external/mesa3d/src/gallium/state_trackers/nine/ |
| D | nine_shader.c | 378 struct sm1_src_param dst_rel[1]; member
3329 sm1_read_dst_param(tx, &insn->dst[i], &insn->dst_rel[i]); in sm1_parse_instruction()
|