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Searched refs:dtpr1 (Results 1 – 13 of 13) sorted by relevance

/external/u-boot/board/ti/ks2_evm/
Dddr3_k2g.c28 .dtpr1 = 0x328341E0ul,
68 .dtpr1 = 0x32845A80ul,
129 .dtpr1 = 0x32834200ul,
Dddr3_cfg.c26 .dtpr1 = 0x12868300ul,
/external/u-boot/arch/arm/mach-keystone/include/mach/
Dddr3.h26 unsigned int dtpr1; member
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dsdram.h83 u32 dtpr1; member
/external/u-boot/drivers/ram/stm32mp1/
Dstm32mp1_ddr.h135 u32 dtpr1; member
Dstm32mp1_ddr_regs.h155 u32 dtpr1; /* 0x38 DRAM Timing Parameters1*/ member
Dstm32mp1_ddr.c144 DDRPHY_REG_TIMING(dtpr1),
/external/u-boot/arch/arm/mach-keystone/
Dddr3_spd.c32 debug_ddr_cfg("dtpr1 0x%08X\n", ptr->dtpr1); in dump_phy_config()
330 spd_cb->phy_cfg.dtpr1 = (spd->t_wlo & 0xf) << 26 | in init_ddr3param()
Dddr3.c50 __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET); in ddr3_init_ddrphy()
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Ddram_sun8i_a23.h182 u32 dtpr1; /* 0x4c dram timing parameters register 1 */ member
Ddram_sun6i.h171 u32 dtpr1; /* 0x38 dram timing parameters register 1 */ member
/external/u-boot/doc/device-tree-bindings/clock/
Drockchip,rk3288-dmc.txt90 dtpr1
/external/u-boot/arch/arm/mach-sunxi/
Ddram_sun6i.c141 (MCTL_TAOND << 0), &mctl_phy->dtpr1); in mctl_channel_init()