Searched refs:dv_reg (Results 1 – 11 of 11) sorted by relevance
93 dv_reg TXIDVER;94 dv_reg TXCONTROL;95 dv_reg TXTEARDOWN;97 dv_reg RXIDVER;98 dv_reg RXCONTROL;99 dv_reg RXTEARDOWN;101 dv_reg TXINTSTATRAW;102 dv_reg TXINTSTATMASKED;103 dv_reg TXINTMASKSET;104 dv_reg TXINTMASKCLEAR;[all …]
542 dv_reg dly = 0xff; in davinci_eth_ch_teardown()543 dv_reg cnt; in davinci_eth_ch_teardown()
22 typedef volatile unsigned int dv_reg; typedef334 dv_reg revid;335 dv_reg rsvd0[71];336 dv_reg ptcmd;337 dv_reg rsvd1;338 dv_reg ptstat;339 dv_reg rsvd2[437];342 dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];343 dv_reg rsvd3[112];344 dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];[all …]
114 dv_reg mmcctl;115 dv_reg mmcclk;116 dv_reg mmcst0;117 dv_reg mmcst1;118 dv_reg mmcim;119 dv_reg mmctor;120 dv_reg mmctod;121 dv_reg mmcblen;122 dv_reg mmcnblk;123 dv_reg mmcnblc;[all …]
30 dv_reg revision;31 dv_reg control;32 dv_reg status;33 dv_reg emulation;34 dv_reg mode;35 dv_reg autoreq;36 dv_reg srpfixtime;37 dv_reg teardown;38 dv_reg intsrc;39 dv_reg intsrc_set;[all …]
18 dv_reg *mux; /* Address of mux register */
93 dv_reg gcr0; /* 0x00 */94 dv_reg gcr1; /* 0x04 */95 dv_reg int0; /* 0x08 */96 dv_reg lvl; /* 0x0c */97 dv_reg flg; /* 0x10 */98 dv_reg pc0; /* 0x14 */99 dv_reg pc1; /* 0x18 */100 dv_reg pc2; /* 0x1c */101 dv_reg pc3; /* 0x20 */102 dv_reg pc4; /* 0x24 */[all …]
30 typedef volatile unsigned int dv_reg; typedef
36 typedef volatile unsigned int dv_reg; typedef
52 const dv_reg *mux = pins[i].mux; in davinci_configure_pin_mux()
21 typedef volatile unsigned int dv_reg; typedef