Searched refs:dvp (Results 1 – 25 of 29) sorted by relevance
12
| /external/libevent/ |
| D | devpoll.c | 172 struct dvpoll dvp; in devpoll_dispatch() local
181 dvp.dp_fds = devpollop->events; in devpoll_dispatch()
182 dvp.dp_nfds = devpollop->nevents; in devpoll_dispatch()
183 dvp.dp_timeout = timeout; in devpoll_dispatch()
187 res = ioctl(devpollop->dpfd, DP_POLL, &dvp); in devpoll_dispatch()
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| /external/u-boot/arch/arm/dts/ |
| D | rk3288-popmetal.dtsi | 78 dvp-supply = <&vcc18_dvp>;
128 vcc18_dvp: vcc18-dvp-regulator {
130 regulator-name = "vcc18-dvp";
136 vcc28_dvp: vcc28-dvp-regulator {
457 dvp {
458 dvp_pwr: dvp-pwr {
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| D | stih407-clock.dtsi | 196 "clk-compo-dvp";
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| D | stih410-clock.dtsi | 203 "clk-compo-dvp",
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| D | rk3288-phycore-som.dtsi | 84 dvp-supply = <&vdd_3v3_io>;
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| D | rk3328.dtsi | 1481 dvp_d2d9_m0:dvp-d2d9-m0 {
1511 dvp_d2d9_m1:dvp-d2d9-m1 {
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| D | rk3288-veyron.dtsi | 215 dvp-supply = <&vcc_18>;
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| /external/python/cpython3/Modules/ |
| D | selectmodule.c | 887 struct dvpoll dvp; in devpoll_poll() local
925 dvp.dp_fds = self->fds; in devpoll_poll()
926 dvp.dp_nfds = self->max_n_fds; in devpoll_poll()
927 dvp.dp_timeout = (int)ms; in devpoll_poll()
936 poll_result = ioctl(self->fd_devpoll, DP_POLL, &dvp); in devpoll_poll()
953 dvp.dp_timeout = (int)ms; in devpoll_poll()
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| /external/llvm/test/MC/Mips/micromips64r6/ |
| D | valid.s | 236 dvp # CHECK: dvp $zero # encoding: [0x00,0x00,0x19,0x7c]
237 dvp $4 # CHECK: dvp $4 # encoding: [0x00,0x04,0x19,0x7c]
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| D | invalid.s | 161 dvp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
162 dvp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
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| /external/libusb-compat/ |
| D | config.sub | 247 | d10v | d30v | dlx | dsp16xx | dvp \
731 dvp)
732 basic_machine=dvp-scei
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| /external/llvm/test/MC/Mips/micromips32r6/ |
| D | valid.s | 316 dvp # CHECK: dvp $zero # encoding: [0x00,0x00,0x19,0x7c]
317 dvp $4 # CHECK: dvp $4 # encoding: [0x00,0x04,0x19,0x7c]
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| D | invalid.s | 136 dvp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
137 dvp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/micromips32r6/ |
| D | valid.txt | 68 0x00 0x11 0x19 0x7c # CHECK: dvp $17
69 0x00 0x00 0x19 0x7c # CHECK: dvp $zero
309 0x00 0x00 0x19 0x7c # CHECK: dvp
310 0x00 0x04 0x19 0x7c # CHECK: dvp $4
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips32r6/ |
| D | valid.s | 365 dvp # CHECK: dvp $zero # encoding: [0x00,0x00,0x19,0x7c]
366 dvp $4 # CHECK: dvp $4 # encoding: [0x00,0x04,0x19,0x7c]
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| D | invalid.s | 139 dvp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
140 dvp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips32r6/ |
| D | valid-mips32r6-el.txt | 93 0x24 0x00 0x71 0x41 # CHECK: dvp $17
94 0x24 0x00 0x60 0x41 # CHECK: dvp $zero
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| D | valid-mips32r6.txt | 71 0x41 0x60 0x00 0x24 # CHECK: dvp $zero
75 0x41 0x71 0x00 0x24 # CHECK: dvp $17
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r6/ |
| D | valid-mips64r6-el.txt | 119 0x24 0x00 0x71 0x41 # CHECK: dvp $17
120 0x24 0x00 0x60 0x41 # CHECK: dvp $zero
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| D | valid-mips64r6.txt | 88 0x41 0x60 0x00 0x24 # CHECK: dvp $zero
94 0x41 0x71 0x00 0x24 # CHECK: dvp $17
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| /external/google-breakpad/autotools/ |
| D | config.sub | 261 | d10v | d30v | dlx | dsp16xx | dvp \
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| /external/expat/conftools/ |
| D | config.sub | 258 | d10v | d30v | dlx | dsp16xx | dvp \
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| /external/llvm/test/MC/Disassembler/Mips/micromips64r6/ |
| D | valid.txt | 236 0x00 0x00 0x19 0x7c # CHECK: dvp
237 0x00 0x04 0x19 0x7c # CHECK: dvp $4
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| /external/llvm/test/MC/Disassembler/Mips/micromips32r6/ |
| D | valid.txt | 301 0x00 0x00 0x19 0x7c # CHECK: dvp
302 0x00 0x04 0x19 0x7c # CHECK: dvp $4
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | Mips32r6InstrInfo.td | 550 class DVP_DESC : DVPEVP_DESC_BASE<"dvp", II_DVP>;
986 def : MipsInstAlias<"dvp", (DVP ZERO), 0>, ISA_MIPS32R6;
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