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Searched refs:effective_cs (Results 1 – 7 of 7) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_leveling.c77 for (effective_cs = 0; effective_cs < NUM_OF_CS; effective_cs++) in ddr3_tip_dynamic_read_leveling()
80 rl_values[effective_cs][bus_num][if_id] = 0; in ddr3_tip_dynamic_read_leveling()
82 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_dynamic_read_leveling()
118 effective_cs, STRESS_NONE, DURATION_SINGLE)); in ddr3_tip_dynamic_read_leveling()
139 (0x301b01 | effective_cs << 2), 0x3c3fef)); in ddr3_tip_dynamic_read_leveling()
239 if_id, effective_cs, bus_num)); in ddr3_tip_dynamic_read_leveling()
250 rl_values[effective_cs][bus_num] in ddr3_tip_dynamic_read_leveling()
290 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_dynamic_read_leveling()
299 data = rl_values[effective_cs][bus_num][if_id]; in ddr3_tip_dynamic_read_leveling()
307 RL_PHY_REG(effective_cs), in ddr3_tip_dynamic_read_leveling()
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Dddr3_training_pbs.c70 CRX_PHY_REG(effective_cs) : in ddr3_tip_pbs()
71 CTX_PHY_REG(effective_cs); in ddr3_tip_pbs()
184 (0x54 + effective_cs * 0x10) : in ddr3_tip_pbs()
185 (0x14 + effective_cs * 0x10); in ddr3_tip_pbs()
191 (0x55 + effective_cs * 0x10) : in ddr3_tip_pbs()
192 (0x15 + effective_cs * 0x10); in ddr3_tip_pbs()
244 (0x54 + effective_cs * 0x10) : in ddr3_tip_pbs()
245 (0x14 + effective_cs * 0x10); in ddr3_tip_pbs()
254 (0x55 + effective_cs * 0x10) : in ddr3_tip_pbs()
255 (0x15 + effective_cs * 0x10); in ddr3_tip_pbs()
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Dddr3_training.c58 u32 effective_cs = 0; variable
1299 ddr3_tip_calc_cs_mask(dev_num, if_id, effective_cs, in ddr3_tip_freq_set()
1908 if (cs_bitmask != effective_cs) { in ddr3_tip_write_cs_result()
1914 (effective_cs * 0x4), in ddr3_tip_write_cs_result()
2019 WL_PHY_REG(effective_cs), in ddr3_tip_ddr3_reset_phy_regs()
2024 RL_PHY_REG(effective_cs), in ddr3_tip_ddr3_reset_phy_regs()
2029 CRX_PHY_REG(effective_cs), phy_reg3_val)); in ddr3_tip_ddr3_reset_phy_regs()
2033 CTX_PHY_REG(effective_cs), phy_reg1_val)); in ddr3_tip_ddr3_reset_phy_regs()
2037 PBS_TX_BCAST_PHY_REG(effective_cs), 0x0)); in ddr3_tip_ddr3_reset_phy_regs()
2041 PBS_RX_BCAST_PHY_REG(effective_cs), 0)); in ddr3_tip_ddr3_reset_phy_regs()
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Dddr3_training_centralization.c93 reg_phy_off = CTX_PHY_REG(effective_cs); in ddr3_tip_centralization()
97 reg_phy_off = CRX_PHY_REG(effective_cs); in ddr3_tip_centralization()
188 effective_cs, pattern_id, in ddr3_tip_centralization()
441 effective_cs, &reg); in ddr3_tip_centralization()
455 effective_cs, reg)); in ddr3_tip_centralization()
511 if ((ddr3_tip_special_rx_run_once_flag & (1 << effective_cs)) == (1 << effective_cs)) in ddr3_tip_special_rx()
514 ddr3_tip_special_rx_run_once_flag |= (1 << effective_cs); in ddr3_tip_special_rx()
626 PBS_RX_PHY_REG(effective_cs, pad_num), in ddr3_tip_special_rx()
636 PBS_RX_PHY_REG(effective_cs, pad_num), in ddr3_tip_special_rx()
650 PBS_RX_PHY_REG(effective_cs, 4), in ddr3_tip_special_rx()
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Dddr3_training_ip_engine.c383 (0x3 | (effective_cs << 26)), 0xc000003)); in ddr3_tip_ip_training()
407 delay_between_burst, rd_mode, effective_cs, STRESS_NONE, in ddr3_tip_ip_training()
459 reg_data = PBS_RX_BCAST_PHY_REG(effective_cs); in ddr3_tip_ip_training()
462 reg_data = PBS_TX_BCAST_PHY_REG(effective_cs); in ddr3_tip_ip_training()
473 reg_data = CTX_PHY_REG(effective_cs); in ddr3_tip_ip_training()
477 reg_data = CRX_PHY_REG(effective_cs); in ddr3_tip_ip_training()
888 (effective_cs << 26); in ddr3_tip_load_pattern_to_mem()
895 ODPG_DATA_CTRL_REG, (0x1 | (effective_cs << 26)), in ddr3_tip_load_pattern_to_mem()
1471 CTX_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
1478 RL_PHY_REG(effective_cs), in ddr3_tip_load_phy_values()
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Dddr3_training_leveling.h12 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
Dddr3_init.h129 extern u32 effective_cs;