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Searched refs:elt2 (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
Dsign_extend.ll88 %elt2 = extractelement <4 x i32> %ext, i32 2
92 store volatile i32 %elt2, i32 addrspace(1)* %out
114 %elt2 = extractelement <4 x i32> %ext, i32 2
118 store volatile i32 %elt2, i32 addrspace(1)* %out
135 %elt2 = extractelement <4 x i32> %ext, i32 2
139 store volatile i32 %elt2, i32 addrspace(1)* %out
158 %elt2 = extractelement <4 x i32> %ext, i32 2
162 store volatile i32 %elt2, i32 addrspace(1)* %out
Dextract-vector-elt-build-vector-combine.ll22 %elt2 = load volatile i32, i32 addrspace(1)* %in
27 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
64 %elt2 = load volatile i32, i32 addrspace(1)* %in
69 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
108 %elt2 = load volatile i32, i32 addrspace(1)* %in
113 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
Dextractelt-to-trunc.ll63 %elt2 = extractelement <4 x i32> %vec, i32 2
64 store i32 %elt2, i32 addrspace(1)* %out
Dds_read2_superreg.ll52 %elt2 = extractelement <4 x float> %val0, i32 2
55 %add0 = fadd float %elt0, %elt2
77 %elt2 = extractelement <3 x float> %val0, i32 2
79 %add0 = fadd float %elt0, %elt2
Dsalu-to-valu.ll327 %elt2 = extractelement <8 x i32> %tmp3, i32 2
335 %add1 = add i32 %add0, %elt2
399 %elt2 = extractelement <16 x i32> %tmp3, i32 2
415 %add1 = add i32 %add0, %elt2
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dextract-vector-elt-build-vector-combine.ll22 %elt2 = load volatile i32, i32 addrspace(1)* %in
27 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
64 %elt2 = load volatile i32, i32 addrspace(1)* %in
69 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
108 %elt2 = load volatile i32, i32 addrspace(1)* %in
113 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
Dsign_extend.ll139 %elt2 = extractelement <4 x i32> %ext, i32 2
143 store volatile i32 %elt2, i32 addrspace(1)* %out
172 %elt2 = extractelement <4 x i32> %ext, i32 2
176 store volatile i32 %elt2, i32 addrspace(1)* %out
198 %elt2 = extractelement <4 x i32> %ext, i32 2
202 store volatile i32 %elt2, i32 addrspace(1)* %out
219 %elt2 = extractelement <4 x i32> %ext, i32 2
223 store volatile i32 %elt2, i32 addrspace(1)* %out
Dextractelt-to-trunc.ll71 %elt2 = extractelement <4 x i32> %vec, i32 2
72 store i32 %elt2, i32 addrspace(1)* %out
Dds_read2_superreg.ll52 %elt2 = extractelement <4 x float> %val0, i32 2
55 %add0 = fadd float %elt0, %elt2
77 %elt2 = extractelement <3 x float> %val0, i32 2
79 %add0 = fadd float %elt0, %elt2
Dreduction.ll190 %elt2 = extractelement <8 x i16> %vec8, i64 2
199 %cmp1 = icmp ult i16 %elt2, %min1
200 %min2 = select i1 %cmp1, i16 %elt2, i16 %min1
281 %elt2 = extractelement <16 x i16> %vec16, i64 2
299 %cmp1 = icmp slt i16 %elt2, %min1
300 %min2 = select i1 %cmp1, i16 %elt2, i16 %min1
Dextract_vector_elt-i16.ll159 %elt2 = extractelement <16 x i16> %load, i32 2
161 store volatile i16 %elt2, i16 addrspace(1)* undef, align 2
Dextract_vector_elt-f16.ll162 %elt2 = extractelement <16 x half> %load, i32 2
164 store volatile half %elt2, half addrspace(1)* undef, align 2
Dsalu-to-valu.ll325 %elt2 = extractelement <8 x i32> %tmp3, i32 2
333 %add1 = add i32 %add0, %elt2
397 %elt2 = extractelement <16 x i32> %tmp3, i32 2
413 %add1 = add i32 %add0, %elt2
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/AMDGPU/
Dreduction.ll29 %elt2 = extractelement <4 x half> %a, i64 2
33 %add2 = fadd fast half %elt2, %add1
73 %elt2 = extractelement <8 x half> %vec8, i64 2
81 %add2 = fadd fast half %elt2, %add1
143 %elt2 = extractelement <16 x half> %vec16, i64 2
159 %add2 = fadd fast half %elt2, %add1
193 %elt2 = extractelement <4 x half> %a, i64 2
197 %add2 = fsub fast half %elt2, %add1
227 %elt2 = extractelement <4 x i16> %a, i64 2
231 %add2 = add i16 %elt2, %add1
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
D2009-08-19-LoadNarrowingMiscompile.ll9 %sroa.store.elt2 = lshr i96 %srcval1, 64
10 %tmp = trunc i96 %sroa.store.elt2 to i64
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
D2009-08-19-LoadNarrowingMiscompile.ll9 %sroa.store.elt2 = lshr i96 %srcval1, 64
10 %tmp = trunc i96 %sroa.store.elt2 to i64
/external/llvm/test/CodeGen/X86/
D2009-08-19-LoadNarrowingMiscompile.ll9 %sroa.store.elt2 = lshr i96 %srcval1, 64
10 %tmp = trunc i96 %sroa.store.elt2 to i64
/external/llvm/test/CodeGen/SystemZ/
Dvec-perm-12.ll35 %elt2 = extractelement <4 x i32> %x, i32 1
39 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
Dvec-combine-02.ll393 %elt2 = extractelement <4 x float> %pack, i32 2
395 %add0 = fadd float %elt0, %elt2
427 %elt2 = extractelement <4 x i32> %pack, i32 2
429 %add0 = add i32 %elt0, %elt2
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dvec-perm-12.ll35 %elt2 = extractelement <4 x i32> %x, i32 1
39 %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
Dvec-combine-02.ll393 %elt2 = extractelement <4 x float> %pack, i32 2
395 %add0 = fadd float %elt0, %elt2
427 %elt2 = extractelement <4 x i32> %pack, i32 2
429 %add0 = add i32 %elt0, %elt2
/external/swiftshader/third_party/subzero/tests_lit/assembler/x86/
Dopcode_register_encodings.ll173 define internal <4 x i32> @test_pinsrd(<4 x i32> %vec, i32 %elt1, i32 %elt2,
176 %elt12 = add i32 %elt1, %elt2
192 %elt2 = trunc i32 %elt2_w to i8
195 %elt12 = add i8 %elt1, %elt2
211 %elt2 = trunc i32 %elt2_w to i16
214 %elt12 = add i16 %elt1, %elt2
/external/webrtc/webrtc/libjingle/xmllite/
Dxmlelement_unittest.cc33 XmlElement elt2(QName("google:test", "first"), true); in TEST() local
34 EXPECT_EQ("<first xmlns=\"google:test\"/>", elt2.Str()); in TEST()
/external/python/cpython2/Tools/compiler/
Dastgen.py250 for elt2 in flatten(elt):
251 l.append(elt2)
/external/llvm/test/Transforms/InstCombine/
Dinsert-extract-shuffle.ll16 %elt2 = extractelement <8 x i16> %in2, i32 0
21 %vec.2 = insertelement <4 x i16> %vec.1, i16 %elt2, i32 2

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