Home
last modified time | relevance | path

Searched refs:emif_ddr_phy_ctlr_1 (Results 1 – 25 of 31) sorted by relevance

12

/external/u-boot/arch/arm/mach-omap2/omap4/
Dsdram_elpida.c45 .emif_ddr_phy_ctlr_1 = 0x049ff808
59 .emif_ddr_phy_ctlr_1 = 0x049ff418
73 .emif_ddr_phy_ctlr_1 = 0x049ff418
87 .emif_ddr_phy_ctlr_1 = 0x049ff418
/external/u-boot/arch/arm/mach-omap2/omap5/
Dsdram.c45 .emif_ddr_phy_ctlr_1 = 0x0E28420d,
64 .emif_ddr_phy_ctlr_1 = 0x0E30400d,
83 .emif_ddr_phy_ctlr_1 = 0x0E28420d,
103 .emif_ddr_phy_ctlr_1 = 0x0024420A,
127 .emif_ddr_phy_ctlr_1 = 0x0034400A,
/external/u-boot/board/ti/am43xx/
Dboard.c163 .emif_ddr_phy_ctlr_1 = 0x0E284006,
196 .emif_ddr_phy_ctlr_1 = 0x0E004008,
222 .emif_ddr_phy_ctlr_1 = 0x0E004008,
245 .emif_ddr_phy_ctlr_1 = 0x0E004008,
268 .emif_ddr_phy_ctlr_1 = 0x0e084008,
294 .emif_ddr_phy_ctlr_1 = 0x00008009,
/external/u-boot/board/ti/ti814x/
Devm.c51 .emif_ddr_phy_ctlr_1 = 0x00000007
60 .emif_ddr_phy_ctlr_1 = 0x00000007
/external/u-boot/board/ti/am335x/
Dboard.c112 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
122 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
204 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
216 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
227 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
238 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
/external/u-boot/board/ti/dra7xx/
Devm.c75 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
100 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
125 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
150 .emif_ddr_phy_ctlr_1 = 0x0E24400E,
175 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
200 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
225 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
250 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
/external/u-boot/board/siemens/draco/
Dboard.c100 PRINTARGS(emif_ddr_phy_ctlr_1); in print_ddr3_timings()
220 draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 = in board_init_ddr()
221 settings.ddr3.emif_ddr_phy_ctlr_1; in board_init_ddr()
Dboard.h42 unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */ member
/external/u-boot/arch/arm/mach-omap2/am33xx/
Dddr.c167 writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1); in config_sdram()
168 writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw); in config_sdram()
316 writel(regs->emif_ddr_phy_ctlr_1, in config_ddr_phy()
318 writel(regs->emif_ddr_phy_ctlr_1, in config_ddr_phy()
Dchilisom.c92 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
/external/u-boot/board/phytec/pcm051/
Dboard.c86 .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
129 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
/external/u-boot/board/compulab/cl-som-am57x/
Dspl.c42 .emif_ddr_phy_ctlr_1 = 0x0e34400b,
110 .emif_ddr_phy_ctlr_1 = 0x0e34400b,
/external/u-boot/board/isee/igep003x/
Dboard.c111 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
121 .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
/external/u-boot/board/gumstix/pepper/
Dboard.c62 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
95 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
/external/u-boot/arch/arm/mach-omap2/
Demif-common.c153 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); in lpddr2_init()
186 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); in emif_update_timings()
218 writel(regs->emif_ddr_phy_ctlr_1, in omap5_ddr3_leveling()
221 writel(regs->emif_ddr_phy_ctlr_1, in omap5_ddr3_leveling()
291 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); in update_hwleveling_output()
292 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); in update_hwleveling_output()
988 regs->emif_ddr_phy_ctlr_1 = in emif_calculate_regs()
1002 print_timing_reg(regs->emif_ddr_phy_ctlr_1); in emif_calculate_regs()
/external/u-boot/board/compulab/cm_t54/
Dspl.c30 .emif_ddr_phy_ctlr_1 = 0x0034400B,
/external/u-boot/board/compulab/cm_t43/
Dspl.c42 .emif_ddr_phy_ctlr_1 = 0x0E004008,
/external/u-boot/board/compulab/cm_t335/
Dspl.c55 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
/external/u-boot/board/BuR/brppt1/
Dboard.c65 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
/external/u-boot/board/ti/ti816x/
Devm.c97 .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
/external/u-boot/board/ti/am57xx/
Dboard.c121 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
185 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
248 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
273 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
/external/u-boot/board/silica/pengwyn/
Dboard.c50 .emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
/external/u-boot/board/eets/pdu001/
Dboard.c181 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
/external/u-boot/board/BuR/brxre1/
Dboard.c76 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
/external/u-boot/board/birdland/bav335x/
Dboard.c151 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,

12