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Searched refs:enablePostRAScheduler (Results 1 – 25 of 33) sorted by relevance

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/external/llvm/lib/CodeGen/
DPostRASchedulerList.cpp107 bool enablePostRAScheduler(
266 bool PostRAScheduler::enablePostRAScheduler( in enablePostRAScheduler() function in PostRAScheduler
278 return ST.enablePostRAScheduler() && in enablePostRAScheduler()
299 if (!enablePostRAScheduler(Fn.getSubtarget(), PassConfig->getOptLevel(), in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DPostRASchedulerList.cpp107 bool enablePostRAScheduler(
266 bool PostRAScheduler::enablePostRAScheduler( in enablePostRAScheduler() function in PostRAScheduler
278 return ST.enablePostRAScheduler() && in enablePostRAScheduler()
299 if (!enablePostRAScheduler(Fn.getSubtarget(), PassConfig->getOptLevel(), in runOnMachineFunction()
DTargetSubtargetInfo.cpp62 bool TargetSubtargetInfo::enablePostRAScheduler() const { in enablePostRAScheduler() function in TargetSubtargetInfo
/external/swiftshader/third_party/LLVM/lib/Target/
DTargetSubtargetInfo.cpp25 bool TargetSubtargetInfo::enablePostRAScheduler( in enablePostRAScheduler() function in TargetSubtargetInfo
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetSubtargetInfo.h57 virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUSubtarget.h91 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
DSPUSubtarget.cpp50 bool SPUSubtarget::enablePostRAScheduler( in enablePostRAScheduler() function in SPUSubtarget
/external/llvm/lib/Target/
DTargetSubtargetInfo.cpp48 bool TargetSubtargetInfo::enablePostRAScheduler() const { in enablePostRAScheduler() function in TargetSubtargetInfo
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeSubtarget.h57 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
DMBlazeSubtarget.cpp56 enablePostRAScheduler(CodeGenOpt::Level OptLevel, in enablePostRAScheduler() function in MBlazeSubtarget
/external/llvm/lib/Target/Hexagon/
DHexagonSubtarget.h109 bool enablePostRAScheduler() const override { return true; } in enablePostRAScheduler() function
/external/llvm/include/llvm/Target/
DTargetSubtargetInfo.h145 virtual bool enablePostRAScheduler() const;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMSubtarget.h251 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
DARMSubtarget.cpp211 bool ARMSubtarget::enablePostRAScheduler( in enablePostRAScheduler() function in ARMSubtarget
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetSubtargetInfo.h172 virtual bool enablePostRAScheduler() const;
/external/llvm/lib/Target/Mips/
DMipsSubtarget.cpp134 bool MipsSubtarget::enablePostRAScheduler() const { return true; } in enablePostRAScheduler() function in MipsSubtarget
DMipsSubtarget.h166 bool enablePostRAScheduler() const override;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCSubtarget.cpp183 bool PPCSubtarget::enablePostRAScheduler() const { return true; } in enablePostRAScheduler() function in PPCSubtarget
DPPCSubtarget.h320 bool enablePostRAScheduler() const override;
/external/llvm/lib/Target/AArch64/
DAArch64Subtarget.h153 bool enablePostRAScheduler() const override { in enablePostRAScheduler() function
/external/llvm/lib/Target/PowerPC/
DPPCSubtarget.cpp189 bool PPCSubtarget::enablePostRAScheduler() const { return true; } in enablePostRAScheduler() function in PPCSubtarget
DPPCSubtarget.h301 bool enablePostRAScheduler() const override;
/external/llvm/lib/Target/ARM/
DARMSubtarget.cpp295 bool ARMSubtarget::enablePostRAScheduler() const { in enablePostRAScheduler() function in ARMSubtarget
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsSubtarget.cpp214 bool MipsSubtarget::enablePostRAScheduler() const { return true; } in enablePostRAScheduler() function in MipsSubtarget
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64Subtarget.h198 bool enablePostRAScheduler() const override { in enablePostRAScheduler() function

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