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Searched refs:enabled_mask (Results 1 – 25 of 33) sorted by relevance

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/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_streamout.c84 if (!sctx->streamout.enabled_mask) in si_streamout_buffers_dirty()
149 unsigned enabled_mask = 0, append_bitmask = 0; in si_set_streamout_targets() local
156 enabled_mask |= 1 << i; in si_set_streamout_targets()
165 sctx->streamout.enabled_mask = enabled_mask; in si_set_streamout_targets()
211 buffers->enabled_mask |= 1u << bufidx; in si_set_streamout_targets()
218 buffers->enabled_mask &= ~(1u << bufidx); in si_set_streamout_targets()
226 buffers->enabled_mask &= ~(1u << bufidx); in si_set_streamout_targets()
385 sctx->streamout.hw_enabled_mask = sctx->streamout.enabled_mask | in si_set_streamout_enable()
386 (sctx->streamout.enabled_mask << 4) | in si_set_streamout_enable()
387 (sctx->streamout.enabled_mask << 8) | in si_set_streamout_enable()
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Dsi_descriptors.c277 unsigned mask = samplers->enabled_mask; in si_sampler_views_begin_new_cs()
534 samplers->enabled_mask |= 1u << slot; in si_set_sampler_view()
551 samplers->enabled_mask &= ~(1u << slot); in si_set_sampler_view()
598 unsigned mask = samplers->enabled_mask; in si_samplers_update_needs_color_decompress_mask()
633 uint mask = images->enabled_mask; in si_image_views_begin_new_cs()
652 if (images->enabled_mask & (1u << slot)) { in si_disable_shader_image()
660 images->enabled_mask &= ~(1u << slot); in si_disable_shader_image()
805 images->enabled_mask |= 1u << slot; in si_set_shader_image()
845 unsigned mask = images->enabled_mask; in si_images_update_needs_color_decompress_mask()
948 unsigned mask = buffers->enabled_mask; in si_buffer_resources_begin_new_cs()
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Dsi_pipe.h263 unsigned enabled_mask; member
271 unsigned enabled_mask; member
346 unsigned enabled_mask; member
Dsi_debug.c733 enabled_constbuf = sctx->const_and_shader_buffers[processor].enabled_mask >> in si_dump_descriptors()
735 enabled_shaderbuf = sctx->const_and_shader_buffers[processor].enabled_mask & in si_dump_descriptors()
739 enabled_samplers = sctx->samplers[processor].enabled_mask; in si_dump_descriptors()
740 enabled_images = sctx->images[processor].enabled_mask; in si_dump_descriptors()
Dsi_hw_context.c274 ctx->streamout.append_bitmask = ctx->streamout.enabled_mask; in si_begin_new_cs()
Dsi_state.h293 unsigned enabled_mask; member
/external/mesa3d/src/gallium/drivers/r600/
Dr600_streamout.c85 unsigned num_bufs = util_bitcount(rctx->streamout.enabled_mask); in r600_streamout_buffers_dirty()
86 unsigned num_bufs_appended = util_bitcount(rctx->streamout.enabled_mask & in r600_streamout_buffers_dirty()
120 unsigned enabled_mask = 0, append_bitmask = 0; in r600_set_streamout_targets() local
134 enabled_mask |= 1 << i; in r600_set_streamout_targets()
142 rctx->streamout.enabled_mask = enabled_mask; in r600_set_streamout_targets()
329 rctx->streamout.hw_enabled_mask = rctx->streamout.enabled_mask | in r600_set_streamout_enable()
330 (rctx->streamout.enabled_mask << 4) | in r600_set_streamout_enable()
331 (rctx->streamout.enabled_mask << 8) | in r600_set_streamout_enable()
332 (rctx->streamout.enabled_mask << 12); in r600_set_streamout_enable()
Dr600_state_common.c484 dst->states.enabled_mask &= ~disable_mask; in r600_bind_sampler_states()
485 dst->states.dirty_mask &= dst->states.enabled_mask; in r600_bind_sampler_states()
486 dst->states.enabled_mask |= new_mask; in r600_bind_sampler_states()
488 dst->states.has_bordercolor_mask &= dst->states.enabled_mask; in r600_bind_sampler_states()
596 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask; in r600_set_vertex_buffers()
597 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask; in r600_set_vertex_buffers()
598 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask; in r600_set_vertex_buffers()
639 remaining_mask = dst->views.enabled_mask & disable_mask; in r600_set_sampler_views()
674 (dst->states.enabled_mask & (1 << i)) && in r600_set_sampler_views()
689 dst->views.enabled_mask &= ~disable_mask; in r600_set_sampler_views()
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Dr600_pipe.h379 uint32_t enabled_mask; member
389 uint32_t enabled_mask; member
415 uint32_t enabled_mask; member
423 uint32_t enabled_mask; /* non-NULL buffers */ member
446 uint32_t enabled_mask; member
470 uint32_t enabled_mask; member
Dr600_hw_context.c396 ctx->vertex_buffer_state.dirty_mask = ctx->vertex_buffer_state.enabled_mask; in r600_begin_new_cs()
404 constbuf->dirty_mask = constbuf->enabled_mask; in r600_begin_new_cs()
405 samplers->views.dirty_mask = samplers->views.enabled_mask; in r600_begin_new_cs()
406 samplers->states.dirty_mask = samplers->states.enabled_mask; in r600_begin_new_cs()
Devergreen_state.c1804 int offset = util_bitcount(rctx->fragment_images.enabled_mask); in evergreen_emit_fragment_buffer_state()
1812 int offset = util_bitcount(rctx->compute_images.enabled_mask); in evergreen_emit_compute_buffer_state()
1894 i += util_bitcount(rctx->fragment_images.enabled_mask); in evergreen_emit_framebuffer_state()
1895 i += util_bitcount(rctx->fragment_buffers.enabled_mask); in evergreen_emit_framebuffer_state()
3956 astate->enabled_mask &= ~(1 << i); in evergreen_set_hw_atomic_buffers()
3964 astate->enabled_mask |= (1 << i); in evergreen_set_hw_atomic_buffers()
3991 old_mask = istate->enabled_mask; in evergreen_set_shader_buffers()
4000 istate->enabled_mask &= ~(1 << i); in evergreen_set_shader_buffers()
4048 istate->enabled_mask |= (1 << i); in evergreen_set_shader_buffers()
4051 istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46; in evergreen_set_shader_buffers()
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/external/mesa3d/src/gallium/drivers/freedreno/
Dfreedreno_state.c105 so->enabled_mask &= ~(1 << index); in fd_set_constant_buffer()
110 so->enabled_mask |= 1 << index; in fd_set_constant_buffer()
143 so->enabled_mask |= BIT(n); in fd_set_shader_buffers()
145 so->enabled_mask &= ~BIT(n); in fd_set_shader_buffers()
157 so->enabled_mask &= ~mask; in fd_set_shader_buffers()
190 so->enabled_mask |= BIT(n); in fd_set_shader_images()
192 so->enabled_mask &= ~BIT(n); in fd_set_shader_images()
204 so->enabled_mask &= ~mask; in fd_set_shader_images()
320 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, count); in fd_set_vertex_buffers()
321 so->count = util_last_bit(so->enabled_mask); in fd_set_vertex_buffers()
Dfreedreno_draw.c183 foreach_bit(i, ctx->shaderbuf[PIPE_SHADER_FRAGMENT].enabled_mask) in fd_draw_vbo()
186 foreach_bit(i, ctx->shaderimg[PIPE_SHADER_FRAGMENT].enabled_mask) { in fd_draw_vbo()
195 foreach_bit(i, ctx->constbuf[PIPE_SHADER_VERTEX].enabled_mask) in fd_draw_vbo()
197 foreach_bit(i, ctx->constbuf[PIPE_SHADER_FRAGMENT].enabled_mask) in fd_draw_vbo()
201 foreach_bit(i, ctx->vtx.vertexbuf.enabled_mask) { in fd_draw_vbo()
471 foreach_bit(i, ctx->shaderbuf[PIPE_SHADER_COMPUTE].enabled_mask) in fd_launch_grid()
474 foreach_bit(i, ctx->shaderimg[PIPE_SHADER_COMPUTE].enabled_mask) { in fd_launch_grid()
484 foreach_bit(i, ctx->constbuf[PIPE_SHADER_COMPUTE].enabled_mask) in fd_launch_grid()
Dfreedreno_context.h71 uint32_t enabled_mask; member
77 uint32_t enabled_mask; member
83 uint32_t enabled_mask; member
90 uint32_t enabled_mask; member
/external/mesa3d/src/gallium/drivers/freedreno/a2xx/
Dfd2_emit.c57 uint32_t enabled_mask = constbuf->enabled_mask; in emit_constants() local
63 constbuf->dirty_mask = enabled_mask; in emit_constants()
66 while (enabled_mask) { in emit_constants()
67 unsigned index = ffs(enabled_mask) - 1; in emit_constants()
103 enabled_mask &= ~(1 << index); in emit_constants()
/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_state.c320 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, in vc4_set_vertex_buffers()
322 so->count = util_last_bit(so->enabled_mask); in vc4_set_vertex_buffers()
395 so->enabled_mask &= ~(1 << index); in vc4_set_constant_buffer()
405 so->enabled_mask |= 1 << index; in vc4_set_constant_buffer()
Dvc4_context.h200 uint32_t enabled_mask; member
207 uint32_t enabled_mask; member
/external/mesa3d/src/gallium/drivers/virgl/
Dvirgl_context.h48 uint32_t enabled_mask; member
Dvirgl_context.c108 uint32_t remaining_mask = tinfo->enabled_mask; in virgl_attach_res_sampler_views()
697 remaining_mask = tinfo->enabled_mask & disable_mask; in virgl_set_sampler_views()
721 tinfo->enabled_mask &= ~disable_mask; in virgl_set_sampler_views()
722 tinfo->enabled_mask |= new_mask; in virgl_set_sampler_views()
/external/mesa3d/src/gallium/drivers/vc5/
Dvc5_context.h161 uint32_t enabled_mask; member
168 uint32_t enabled_mask; member
Dvc5_state.c259 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, in vc5_set_vertex_buffers()
261 so->count = util_last_bit(so->enabled_mask); in vc5_set_vertex_buffers()
410 so->enabled_mask &= ~(1 << index); in vc5_set_constant_buffer()
415 so->enabled_mask |= 1 << index; in vc5_set_constant_buffer()
/external/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_context.h79 uint32_t enabled_mask; member
Detnaviv_state.c412 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb, start_slot, num_buffers); in etna_set_vertex_buffers()
413 so->count = util_last_bit(so->enabled_mask); in etna_set_vertex_buffers()
/external/mesa3d/src/gallium/drivers/freedreno/a5xx/
Dfd5_image.c210 so->dirty_mask &= so->enabled_mask; in fd5_emit_images()
Dfd5_emit.c377 unsigned count = util_last_bit(so->enabled_mask); in emit_ssbos()
779 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_FRAGMENT].enabled_mask ? in fd5_emit_state()
826 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_COMPUTE].enabled_mask ? in fd5_emit_cs_state()

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