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/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/
Dexact.ll11 ; CHECK: ashr exact i32 %x, 3
13 %y = sdiv exact i32 %x, 8
30 %y = sdiv exact i32 %x, 3
49 %y = sdiv exact i32 %x, 3
57 %y = udiv exact i32 %x, %w
63 ; CHECK: %z = lshr exact i32 %x, %w
67 %z = udiv exact i32 %x, %y
72 ; CHECK: %B = ashr exact i64 %A, 2
85 %A = ashr exact i64 %X, 2 ; X/4
94 %Y = ashr exact i64 %X, 2 ; x / 4
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dexact.ll15 ; CHECK-NEXT: [[Y:%.*]] = ashr exact i32 %x, 3
18 %y = sdiv exact i32 %x, 8
24 ; CHECK-NEXT: [[Y:%.*]] = ashr exact <2 x i32> %x, <i32 7, i32 7>
27 %y = sdiv exact <2 x i32> %x, <i32 128, i32 128>
46 %y = sdiv exact i32 %x, 3
67 %y = sdiv exact i32 %x, 3
76 %y = udiv exact i32 %x, %w
83 ; CHECK-NEXT: [[Z:%.*]] = lshr exact i32 %x, %w
87 %z = udiv exact i32 %x, %y
94 ; CHECK-NEXT: [[B:%.*]] = ashr exact i64 [[A]], 2
[all …]
Dcanonicalize-signed-truncation-check.ll23 %tmp1 = ashr exact i8 %tmp0, 5
36 %tmp1 = ashr exact i65 %tmp0, 1
52 %tmp1 = ashr exact <2 x i8> %tmp0, <i8 5, i8 5>
60 ; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <2 x i8> [[TMP0]], <i8 5, i8 6>
65 %tmp1 = ashr exact <2 x i8> %tmp0, <i8 5, i8 6>
73 ; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <3 x i8> [[TMP0]], <i8 5, i8 5, i8 5>
78 %tmp1 = ashr exact <3 x i8> %tmp0, <i8 5, i8 5, i8 5>
86 ; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <3 x i8> [[TMP0]], <i8 5, i8 undef, i8 5>
91 %tmp1 = ashr exact <3 x i8> %tmp0, <i8 5, i8 undef, i8 5>
99 ; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <3 x i8> [[TMP0]], <i8 5, i8 undef, i8 5>
[all …]
Dcanonicalize-lack-of-signed-truncation-check.ll23 %tmp1 = ashr exact i8 %tmp0, 5
36 %tmp1 = ashr exact i65 %tmp0, 1
52 %tmp1 = ashr exact <2 x i8> %tmp0, <i8 5, i8 5>
60 ; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <2 x i8> [[TMP0]], <i8 5, i8 6>
65 %tmp1 = ashr exact <2 x i8> %tmp0, <i8 5, i8 6>
73 ; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <3 x i8> [[TMP0]], <i8 5, i8 5, i8 5>
78 %tmp1 = ashr exact <3 x i8> %tmp0, <i8 5, i8 5, i8 5>
86 ; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <3 x i8> [[TMP0]], <i8 5, i8 undef, i8 5>
91 %tmp1 = ashr exact <3 x i8> %tmp0, <i8 5, i8 undef, i8 5>
99 ; CHECK-NEXT: [[TMP1:%.*]] = ashr exact <3 x i8> [[TMP0]], <i8 5, i8 undef, i8 5>
[all …]
Dicmp-shr-lt-gt.ll1780 %s = lshr exact i4 %x, 1
1790 %s = lshr exact i4 %x, 1
1800 %s = lshr exact i4 %x, 1
1810 %s = lshr exact i4 %x, 1
1820 %s = lshr exact i4 %x, 1
1830 %s = lshr exact i4 %x, 1
1840 %s = lshr exact i4 %x, 1
1849 %s = lshr exact i4 %x, 1
1858 %s = lshr exact i4 %x, 1
1867 %s = lshr exact i4 %x, 1
[all …]
Dicmp-shr.ll101 %shr = ashr exact i8 128, %a
111 %shr = ashr exact i8 128, %a
121 %shr = lshr exact i8 126, %a
131 %shr = lshr exact i8 126, %a
141 %shr = lshr exact i8 -128, %a
161 %shr = lshr exact i8 -128, %a
181 %shr = ashr exact i8 -128, %a
191 %shr = ashr exact i8 -128, %a
201 %shr = lshr exact i8 4, %a
211 %shr = lshr exact i8 4, %a
[all …]
/external/llvm/test/Transforms/InstCombine/
Dexact.ll15 ; CHECK-NEXT: [[Y:%.*]] = ashr exact i32 %x, 3
18 %y = sdiv exact i32 %x, 8
24 ; CHECK-NEXT: [[Y:%.*]] = ashr exact <2 x i32> %x, <i32 7, i32 7>
27 %y = sdiv exact <2 x i32> %x, <i32 128, i32 128>
46 %y = sdiv exact i32 %x, 3
67 %y = sdiv exact i32 %x, 3
76 %y = udiv exact i32 %x, %w
83 ; CHECK-NEXT: [[Z:%.*]] = lshr exact i32 %x, %w
87 %z = udiv exact i32 %x, %y
94 ; CHECK-NEXT: [[B:%.*]] = ashr exact i64 [[A]], 2
[all …]
Dicmp-shr.ll72 %shr = ashr exact i8 128, %a
80 %shr = ashr exact i8 128, %a
88 %shr = lshr exact i8 126, %a
96 %shr = lshr exact i8 126, %a
104 %shr = lshr exact i8 -128, %a
120 %shr = lshr exact i8 -128, %a
136 %shr = ashr exact i8 -128, %a
144 %shr = ashr exact i8 -128, %a
152 %shr = lshr exact i8 4, %a
160 %shr = lshr exact i8 4, %a
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Dsext-in-reg.ll11 %conv1 = ashr exact i64 %sext, 56
13 %conv4 = ashr exact i64 %sext1, 56
29 %conv1 = ashr exact i64 %sext, 32
31 %conv4 = ashr exact i64 %sext1, 32
47 %conv1 = ashr exact i64 %sext, 48
49 %conv4 = ashr exact i64 %sext1, 48
65 %conv1 = ashr exact i32 %sext, 24
67 %conv4 = ashr exact i32 %sext1, 24
83 %conv1 = ashr exact i32 %sext, 16
85 %conv4 = ashr exact i32 %sext1, 16
[all …]
/external/llvm/test/CodeGen/NVPTX/
Dsext-in-reg.ll11 %conv1 = ashr exact i64 %sext, 56
13 %conv4 = ashr exact i64 %sext1, 56
29 %conv1 = ashr exact i64 %sext, 32
31 %conv4 = ashr exact i64 %sext1, 32
47 %conv1 = ashr exact i64 %sext, 48
49 %conv4 = ashr exact i64 %sext1, 48
65 %conv1 = ashr exact i32 %sext, 24
67 %conv4 = ashr exact i32 %sext1, 24
83 %conv1 = ashr exact i32 %sext, 16
85 %conv4 = ashr exact i32 %sext1, 16
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dmul64-sext.ll10 %v4 = ashr exact i64 %v3, 32
12 %v6 = ashr exact i64 %v5, 32
26 %v6 = ashr exact i64 %v5, 32
38 %v4 = ashr exact i64 %v3, 32
40 %v6 = ashr exact i64 %v5, 48
66 %v5 = ashr exact i64 %v4, 32
68 %v7 = ashr exact i64 %v6, 32
82 %v5 = ashr exact i64 %v4, 32
97 %v5 = ashr exact i64 %v4, 32
99 %v7 = ashr exact i64 %v6, 32
[all …]
Dmul64.ll40 %v3 = ashr exact i32 %v2, 16
70 %v4 = ashr exact i32 %v3, 16
86 %v4 = ashr exact i32 %v3, 16
101 %v3 = ashr exact i32 %v2, 16
178 %v1 = ashr exact i64 %v0, 32
180 %v3 = ashr exact i64 %v2, 48
192 %v1 = ashr exact i64 %v0, 32
207 %v1 = ashr exact i64 %v0, 32
211 %v5 = ashr exact i32 %v4, 16
225 %v2 = ashr exact i64 %v1, 48
[all …]
/external/llvm/test/Transforms/InstSimplify/
Dshr-nop.ll20 %shr = lshr exact i8 0, %a
29 %shr = ashr exact i8 0, %a
47 %shr = lshr exact i8 0, %a
56 %shr = ashr exact i8 0, %a
83 %shr = lshr exact i8 128, %a
92 %shr = ashr exact i8 -128, %a
110 %shr = lshr exact i8 128, %a
119 %shr = ashr exact i8 -128, %a
218 %shr = ashr exact i8 -1, %a
227 %shr = ashr exact i8 -1, %a
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/
Dshr-nop.ll20 %shr = lshr exact i8 0, %a
29 %shr = ashr exact i8 0, %a
47 %shr = lshr exact i8 0, %a
56 %shr = ashr exact i8 0, %a
83 %shr = lshr exact i8 128, %a
92 %shr = ashr exact i8 -128, %a
110 %shr = lshr exact i8 128, %a
119 %shr = ashr exact i8 -128, %a
218 %shr = ashr exact i8 -1, %a
227 %shr = ashr exact i8 -1, %a
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/IndVarSimplify/
Dstrengthen-overflow.ll107 define hidden void @test.shl.exact.equal() {
108 ; CHECK-LABEL: @test.shl.exact.equal
117 ; CHECK: %shr1 = ashr exact i32 %shl, 1
119 ; CHECK: %shr2 = lshr exact i32 %shl, 1
128 define hidden void @test.shl.exact.greater() {
129 ; CHECK-LABEL: @test.shl.exact.greater
138 ; CHECK: %shr1 = ashr exact i32 %shl, 2
140 ; CHECK: %shr2 = lshr exact i32 %shl, 2
149 define hidden void @test.shl.exact.unbound(i32 %arg) {
150 ; CHECK-LABEL: @test.shl.exact.unbound
[all …]
/external/bcc/src/cc/frontends/p4/test/testprograms/
Dbasic_routing.p4126 standard_metadata.ingress_port : exact;
140 ingress_metadata.bd : exact;
155 ingress_metadata.vrf : exact;
156 ipv4.dstAddr : exact;
167 ingress_metadata.vrf : exact;
168 ipv4.dstAddr : exact; // lpm not supported
183 ingress_metadata.nexthop_index : exact;
219 ingress_metadata.nexthop_index : exact;
/external/swiftshader/third_party/LLVM/test/Assembler/
Dflags.ll102 ; CHECK: %z = sdiv exact i64 %x, %y
103 %z = sdiv exact i64 %x, %y
114 ; CHECK: %z = udiv exact i64 %x, %y
115 %z = udiv exact i64 %x, %y
132 ; CHECK: %z = ashr exact i64 %x, %y
133 %z = ashr exact i64 %x, %y
144 ; CHECK: %z = lshr exact i64 %x, %y
145 %z = lshr exact i64 %x, %y
177 ; CHECK: ret i64 sdiv exact (i64 ptrtoint (i64* @addr to i64), i64 91)
178 ret i64 sdiv exact (i64 ptrtoint (i64* @addr to i64), i64 91)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Assembler/
Dflags.ll103 ; CHECK: %z = sdiv exact i64 %x, %y
104 %z = sdiv exact i64 %x, %y
115 ; CHECK: %z = udiv exact i64 %x, %y
116 %z = udiv exact i64 %x, %y
133 ; CHECK: %z = ashr exact i64 %x, %y
134 %z = ashr exact i64 %x, %y
145 ; CHECK: %z = lshr exact i64 %x, %y
146 %z = lshr exact i64 %x, %y
178 ; CHECK: ret i64 sdiv exact (i64 ptrtoint (i64* @addr to i64), i64 91)
179 ret i64 sdiv exact (i64 ptrtoint (i64* @addr to i64), i64 91)
[all …]
/external/llvm/test/Assembler/
Dflags.ll103 ; CHECK: %z = sdiv exact i64 %x, %y
104 %z = sdiv exact i64 %x, %y
115 ; CHECK: %z = udiv exact i64 %x, %y
116 %z = udiv exact i64 %x, %y
133 ; CHECK: %z = ashr exact i64 %x, %y
134 %z = ashr exact i64 %x, %y
145 ; CHECK: %z = lshr exact i64 %x, %y
146 %z = lshr exact i64 %x, %y
178 ; CHECK: ret i64 sdiv exact (i64 ptrtoint (i64* @addr to i64), i64 91)
179 ret i64 sdiv exact (i64 ptrtoint (i64* @addr to i64), i64 91)
[all …]
/external/llvm/test/CodeGen/X86/
Dshift-combine.ll25 %shr = ashr exact i32 %sub, 3
35 %shr = ashr exact i32 %sub, 3
45 %shr = ashr exact i32 %sub, 2
55 %shr = lshr exact i32 %sub, 3
65 %shr = lshr exact i32 %sub, 3
75 %shr = lshr exact i32 %sub, 2
Dsar_fold.ll8 %2 = ashr exact i32 %1, 15
17 %2 = ashr exact i32 %1, 17
26 %2 = ashr exact i32 %1, 23
35 %2 = ashr exact i32 %1, 25
Dsar_fold64.ll8 %2 = ashr exact i64 %1, 47
18 %2 = ashr exact i64 %1, 49
28 %2 = ashr exact i64 %1, 55
38 %2 = ashr exact i64 %1, 57
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dsar_fold.ll8 %2 = ashr exact i32 %1, 15
17 %2 = ashr exact i32 %1, 17
26 %2 = ashr exact i32 %1, 23
35 %2 = ashr exact i32 %1, 25
/external/skqp/src/utils/
DSkInterpolator.cpp100 bool exact = true; in timeToT() local
114 exact = false; in timeToT()
120 if (exact) { in timeToT()
127 *exactPtr = exact; in timeToT()
187 bool exact; in timeToValues() local
188 Result result = timeToT(time, &T, &index, &exact); in timeToValues()
192 if (exact) { in timeToValues()
/external/skia/src/utils/
DSkInterpolator.cpp100 bool exact = true; in timeToT() local
114 exact = false; in timeToT()
120 if (exact) { in timeToT()
127 *exactPtr = exact; in timeToT()
187 bool exact; in timeToValues() local
188 Result result = timeToT(time, &T, &index, &exact); in timeToValues()
192 if (exact) { in timeToValues()

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