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/external/llvm/test/CodeGen/SPARC/
DLeonFixFSMULDPassUT.ll5 ; CHECK: fstod %f21, %f3
16 …%mul = tail call double asm sideeffect "fsmuld $0, $1, $2", "={f20},{f21},{f8}"(float* %a, float* …
23 ; CHECK: fstod %f21, %f3
28 …%mul = tail call double asm sideeffect "fsmuld $0, $1, $2", "={f20},{f21},{f8}"(float* %a, float* …
DLeonReplaceFMULSPassUT.ll5 ; CHECK: fstod %f21, %f3
16 …%mul = tail call double asm sideeffect "fmuls $0, $1, $2", "={f20},{f21},{f8}"(float* %a, float* %…
/external/linux-kselftest/tools/testing/selftests/powerpc/include/
Dfpu_asm.h25 stfd f21,(stack_size + STACK_FRAME_MIN_SIZE - 80)(%r1); \
45 lfd f21,(stack_size + STACK_FRAME_MIN_SIZE - 80)(%r1); \
66 lfd f21,56(r3)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SPARC/
Dinlineasm-bad.ll5 ; CHECK: error: couldn't allocate input reg for constraint '{f21}'
10 …tail call void asm sideeffect "faddd $0,$1,$2", "{f21},{f0},{f0}"(double 9.0, double 10.0, double …
/external/llvm/test/MC/Disassembler/Mips/mips32/
Dvalid-xfail-mips32.txt5 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips32/
Dvalid-xfail-mips32.txt5 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
/external/llvm/test/CodeGen/PowerPC/
Dvsx-spill.ll10 …0},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f2…
31 …0},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f2…
51 …0},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f2…
/external/llvm/test/MC/Disassembler/Mips/mips64/
Dvalid-mips64-xfail.txt5 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
39 0x46 0xde 0xa8 0x3b # CHECK: c.ngl.ps $f21, $f30
42 0x46 0xc8 0xaf 0x36 # CHECK: c.ole.ps $fcc7, $f21, $f8
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64/
Dvalid-mips64-xfail.txt5 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
39 0x46 0xde 0xa8 0x3b # CHECK: c.ngl.ps $f21, $f30
42 0x46 0xc8 0xaf 0x36 # CHECK: c.ole.ps $fcc7, $f21, $f8
/external/llvm/test/MC/Disassembler/Mips/mips4/
Dvalid-xfail-mips4.txt5 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
/external/llvm/test/CodeGen/Mips/
Dno-odd-spreg-msa.ll26 …~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
60 …~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
90 …~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
118 …~{$f11},~{$f12},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
Dno-odd-spreg.ll24 …~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
48 …~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dno-odd-spreg-msa.ll26 …~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
60 …~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
90 …~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
118 …~{$f11},~{$f12},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{…
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dvsx-spill.ll17 …0},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f2…
50 …0},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f2…
81 …0},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f2…
/external/llvm/test/MC/ARM/
Dsymbol-variants.s71 .word f21(tlsldo)
73 @CHECK: 54 R_ARM_TLS_LDO32 f21
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dsymbol-variants.s71 .word f21(tlsldo)
73 @CHECK: 54 R_ARM_TLS_LDO32 f21
/external/testng/src/test/java/test/thread/
DTest2Test.java8 public void f21() { in f21() method in Test2Test
/external/libjpeg-turbo/simd/mips/
Djsimd_dspr2_asm.h81 #define f21 $f21 macro
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r3/
Dvalid-xfail-mips64r3.txt5 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
/external/llvm/test/MC/Disassembler/Mips/mips64r3/
Dvalid-xfail-mips64r3.txt5 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r5/
Dvalid-xfail-mips64r5.txt5 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
/external/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-xfail-mips64r2.txt5 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
/external/llvm/test/MC/Disassembler/Mips/mips64r5/
Dvalid-xfail-mips64r5.txt5 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/mips64r2/
Dvalid-xfail-mips64r2.txt5 0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21
11 0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16
26 0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30
/external/bcc/src/cc/frontends/p4/test/testprograms/
Dbitfields.p425 f21 : 21;

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