1 #if !defined (__GFX9_GB_REG_H__) 2 #define __GFX9_GB_REG_H__ 3 4 /* 5 * Copyright © 2017 Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining 9 * a copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 18 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 19 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 20 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 23 * USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * The above copyright notice and this permission notice (including the 26 * next paragraph) shall be included in all copies or substantial portions 27 * of the Software. 28 */ 29 30 #include "util/u_endian.h" 31 32 #if defined(PIPE_ARCH_LITTLE_ENDIAN) 33 #define LITTLEENDIAN_CPU 34 #elif defined(PIPE_ARCH_BIG_ENDIAN) 35 #define BIGENDIAN_CPU 36 #endif 37 38 // 39 // Make sure the necessary endian defines are there. 40 // 41 #if defined(LITTLEENDIAN_CPU) 42 #elif defined(BIGENDIAN_CPU) 43 #else 44 #error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined" 45 #endif 46 47 union GB_ADDR_CONFIG { 48 struct { 49 #if defined(LITTLEENDIAN_CPU) 50 unsigned int NUM_PIPES : 3; 51 unsigned int PIPE_INTERLEAVE_SIZE : 3; 52 unsigned int MAX_COMPRESSED_FRAGS : 2; 53 unsigned int BANK_INTERLEAVE_SIZE : 3; 54 unsigned int : 1; 55 unsigned int NUM_BANKS : 3; 56 unsigned int : 1; 57 unsigned int SHADER_ENGINE_TILE_SIZE : 3; 58 unsigned int NUM_SHADER_ENGINES : 2; 59 unsigned int NUM_GPUS : 3; 60 unsigned int MULTI_GPU_TILE_SIZE : 2; 61 unsigned int NUM_RB_PER_SE : 2; 62 unsigned int ROW_SIZE : 2; 63 unsigned int NUM_LOWER_PIPES : 1; 64 unsigned int SE_ENABLE : 1; 65 #elif defined(BIGENDIAN_CPU) 66 unsigned int SE_ENABLE : 1; 67 unsigned int NUM_LOWER_PIPES : 1; 68 unsigned int ROW_SIZE : 2; 69 unsigned int NUM_RB_PER_SE : 2; 70 unsigned int MULTI_GPU_TILE_SIZE : 2; 71 unsigned int NUM_GPUS : 3; 72 unsigned int NUM_SHADER_ENGINES : 2; 73 unsigned int SHADER_ENGINE_TILE_SIZE : 3; 74 unsigned int : 1; 75 unsigned int NUM_BANKS : 3; 76 unsigned int : 1; 77 unsigned int BANK_INTERLEAVE_SIZE : 3; 78 unsigned int MAX_COMPRESSED_FRAGS : 2; 79 unsigned int PIPE_INTERLEAVE_SIZE : 3; 80 unsigned int NUM_PIPES : 3; 81 #endif 82 } bitfields, bits; 83 unsigned int u32All; 84 signed int i32All; 85 float f32All; 86 }; 87 88 #endif 89 90