| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/ |
| D | log-exp-intrinsic.ll | 4 declare double @llvm.log.f64(double)
5 declare double @llvm.exp.f64(double)
6 declare double @llvm.log2.f64(double)
7 declare double @llvm.exp2.f64(double)
13 %1 = call double @llvm.exp.f64(double %a)
14 %2 = call reassoc double @llvm.log.f64(double %1)
20 ; CHECK-NEXT: [[TMP1:%.*]] = call reassoc double @llvm.exp.f64(double [[A:%.*]])
21 ; CHECK-NEXT: [[TMP2:%.*]] = call double @llvm.log.f64(double [[TMP1]])
24 %1 = call reassoc double @llvm.exp.f64(double %a)
25 %2 = call double @llvm.log.f64(double %1)
[all …]
|
| /external/llvm/test/MC/ARM/ |
| D | single-precision-fp.s | 5 vadd.f64 d0, d1, d2
6 vsub.f64 d2, d3, d4
7 vdiv.f64 d4, d5, d6
8 vmul.f64 d6, d7, d8
9 vnmul.f64 d8, d9, d10
11 @ CHECK-ERRORS-NEXT: vadd.f64 d0, d1, d2
13 @ CHECK-ERRORS-NEXT: vsub.f64 d2, d3, d4
15 @ CHECK-ERRORS-NEXT: vdiv.f64 d4, d5, d6
17 @ CHECK-ERRORS-NEXT: vmul.f64 d6, d7, d8
19 @ CHECK-ERRORS-NEXT: vnmul.f64 d8, d9, d10
[all …]
|
| D | fp-armv8.s | 5 vcvtt.f64.f16 d3, s1
6 @ CHECK: vcvtt.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xee]
7 vcvtt.f16.f64 s5, d12
8 @ CHECK: vcvtt.f16.f64 s5, d12 @ encoding: [0xcc,0x2b,0xf3,0xee]
10 vcvtb.f64.f16 d3, s1
11 @ CHECK: vcvtb.f64.f16 d3, s1 @ encoding: [0x60,0x3b,0xb2,0xee]
12 vcvtb.f16.f64 s4, d1
13 @ CHECK: vcvtb.f16.f64 s4, d1 @ encoding: [0x41,0x2b,0xb3,0xee]
15 vcvttge.f64.f16 d3, s1
16 @ CHECK: vcvttge.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xae]
[all …]
|
| D | thumb-fp-armv8.s | 5 vcvtt.f64.f16 d3, s1
6 @ CHECK: vcvtt.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0xe0,0x3b]
7 vcvtt.f16.f64 s5, d12
8 @ CHECK: vcvtt.f16.f64 s5, d12 @ encoding: [0xf3,0xee,0xcc,0x2b]
10 vcvtb.f64.f16 d3, s1
11 @ CHECK: vcvtb.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0x60,0x3b]
12 vcvtb.f16.f64 s4, d1
13 @ CHECK: vcvtb.f16.f64 s4, d1 @ encoding: [0xb3,0xee,0x41,0x2b]
16 vcvttge.f64.f16 d3, s1
17 @ CHECK: vcvttge.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0xe0,0x3b]
[all …]
|
| D | directive-arch_extension-fp.s | 35 vselgt.f64 d0, d0, d0
37 vselge.f64 d0, d0, d0
39 vseleq.f64 d0, d0, d0
41 vselvs.f64 d0, d0, d0
43 vmaxnm.f64 d0, d0, d0
45 vminnm.f64 d0, d0, d0
48 vcvtb.f64.f16 d0, s0
50 vcvtb.f16.f64 s0, d0
52 vcvtt.f64.f16 d0, s0
54 vcvtt.f16.f64 s0, d0
[all …]
|
| D | directive-arch_extension-simd.s | 24 vmaxnm.f64 d0, d0, d0
26 vminnm.f64 d0, d0, d0
33 vcvta.s32.f64 s0, d0
35 vcvta.u32.f64 s0, d0
41 vcvtn.s32.f64 s0, d0
43 vcvtn.u32.f64 s0, d0
49 vcvtp.s32.f64 s0, d0
51 vcvtp.u32.f64 s0, d0
57 vcvtm.s32.f64 s0, d0
59 vcvtm.u32.f64 s0, d0
[all …]
|
| D | simple-fp-encoding.s | 3 vadd.f64 d16, d17, d16
5 @ CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
8 vsub.f64 d16, d17, d16
10 @ CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee]
13 vdiv.f64 d16, d17, d16
16 vdiv.f64 d5, d7
18 @ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
21 @ CHECK: vdiv.f64 d5, d5, d7 @ encoding: [0x07,0x5b,0x85,0xee]
24 vmul.f64 d16, d17, d16
25 vmul.f64 d20, d17
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | single-precision-fp.s | 5 vadd.f64 d0, d1, d2
6 vsub.f64 d2, d3, d4
7 vdiv.f64 d4, d5, d6
8 vmul.f64 d6, d7, d8
9 vnmul.f64 d8, d9, d10
11 @ CHECK-ERRORS-NEXT: vadd.f64 d0, d1, d2
13 @ CHECK-ERRORS-NEXT: vsub.f64 d2, d3, d4
15 @ CHECK-ERRORS-NEXT: vdiv.f64 d4, d5, d6
17 @ CHECK-ERRORS-NEXT: vmul.f64 d6, d7, d8
19 @ CHECK-ERRORS-NEXT: vnmul.f64 d8, d9, d10
[all …]
|
| D | thumb-fp-armv8.s | 5 vcvtt.f64.f16 d3, s1
6 @ CHECK: vcvtt.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0xe0,0x3b]
7 vcvtt.f16.f64 s5, d12
8 @ CHECK: vcvtt.f16.f64 s5, d12 @ encoding: [0xf3,0xee,0xcc,0x2b]
10 vcvtb.f64.f16 d3, s1
11 @ CHECK: vcvtb.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0x60,0x3b]
12 vcvtb.f16.f64 s4, d1
13 @ CHECK: vcvtb.f16.f64 s4, d1 @ encoding: [0xb3,0xee,0x41,0x2b]
16 vcvttge.f64.f16 d3, s1
17 @ CHECK: vcvttge.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0xe0,0x3b]
[all …]
|
| D | fp-armv8.s | 5 vcvtt.f64.f16 d3, s1
6 @ CHECK: vcvtt.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xee]
7 vcvtt.f16.f64 s5, d12
8 @ CHECK: vcvtt.f16.f64 s5, d12 @ encoding: [0xcc,0x2b,0xf3,0xee]
10 vcvtb.f64.f16 d3, s1
11 @ CHECK: vcvtb.f64.f16 d3, s1 @ encoding: [0x60,0x3b,0xb2,0xee]
12 vcvtb.f16.f64 s4, d1
13 @ CHECK: vcvtb.f16.f64 s4, d1 @ encoding: [0x41,0x2b,0xb3,0xee]
15 vcvttge.f64.f16 d3, s1
16 @ CHECK: vcvttge.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xae]
[all …]
|
| D | directive-arch_extension-fp.s | 35 vselgt.f64 d0, d0, d0
37 vselge.f64 d0, d0, d0
39 vseleq.f64 d0, d0, d0
41 vselvs.f64 d0, d0, d0
43 vmaxnm.f64 d0, d0, d0
45 vminnm.f64 d0, d0, d0
48 vcvtb.f64.f16 d0, s0
50 vcvtb.f16.f64 s0, d0
52 vcvtt.f64.f16 d0, s0
54 vcvtt.f16.f64 s0, d0
[all …]
|
| D | directive-arch_extension-simd.s | 24 vmaxnm.f64 d0, d0, d0
26 vminnm.f64 d0, d0, d0
33 vcvta.s32.f64 s0, d0
35 vcvta.u32.f64 s0, d0
41 vcvtn.s32.f64 s0, d0
43 vcvtn.u32.f64 s0, d0
49 vcvtp.s32.f64 s0, d0
51 vcvtp.u32.f64 s0, d0
57 vcvtm.s32.f64 s0, d0
59 vcvtm.u32.f64 s0, d0
[all …]
|
| D | simple-fp-encoding.s | 3 vadd.f64 d16, d17, d16
5 @ CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
8 vsub.f64 d16, d17, d16
10 @ CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee]
13 vdiv.f64 d16, d17, d16
16 vdiv.f64 d5, d7
18 @ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
21 @ CHECK: vdiv.f64 d5, d5, d7 @ encoding: [0x07,0x5b,0x85,0xee]
24 vmul.f64 d16, d17, d16
25 vmul.f64 d20, d17
[all …]
|
| /external/capstone/suite/MC/ARM/ |
| D | thumb-fp-armv8.s.cs | 2 0xb2,0xee,0xe0,0x3b = vcvtt.f64.f16 d3, s1
3 0xf3,0xee,0xcc,0x2b = vcvtt.f16.f64 s5, d12
4 0xb2,0xee,0x60,0x3b = vcvtb.f64.f16 d3, s1
5 0xb3,0xee,0x41,0x2b = vcvtb.f16.f64 s4, d1
6 0xb2,0xee,0xe0,0x3b = vcvttge.f64.f16 d3, s1
7 0xf3,0xee,0xcc,0x2b = vcvttgt.f16.f64 s5, d12
8 0xb2,0xee,0x60,0x3b = vcvtbeq.f64.f16 d3, s1
9 0xb3,0xee,0x41,0x2b = vcvtblt.f16.f64 s4, d1
11 0xbc,0xfe,0xc3,0x1b = vcvta.s32.f64 s2, d3
13 0xbd,0xfe,0xe7,0x3b = vcvtn.s32.f64 s6, d23
[all …]
|
| D | fp-armv8.s.cs | 2 0xe0,0x3b,0xb2,0xee = vcvtt.f64.f16 d3, s1
3 0xcc,0x2b,0xf3,0xee = vcvtt.f16.f64 s5, d12
4 0x60,0x3b,0xb2,0xee = vcvtb.f64.f16 d3, s1
5 0x41,0x2b,0xb3,0xee = vcvtb.f16.f64 s4, d1
6 0xe0,0x3b,0xb2,0xae = vcvttge.f64.f16 d3, s1
7 0xcc,0x2b,0xf3,0xce = vcvttgt.f16.f64 s5, d12
8 0x60,0x3b,0xb2,0x0e = vcvtbeq.f64.f16 d3, s1
9 0x41,0x2b,0xb3,0xbe = vcvtblt.f16.f64 s4, d1
11 0xc3,0x1b,0xbc,0xfe = vcvta.s32.f64 s2, d3
13 0xe7,0x3b,0xbd,0xfe = vcvtn.s32.f64 s6, d23
[all …]
|
| D | simple-fp-encoding.s.cs | 2 0xa0,0x0b,0x71,0xee = vadd.f64 d16, d17, d16
4 0xe0,0x0b,0x71,0xee = vsub.f64 d16, d17, d16
6 0xa0,0x0b,0xc1,0xee = vdiv.f64 d16, d17, d16
9 0x07,0x5b,0x85,0xee = vdiv.f64 d5, d5, d7
10 0xa0,0x0b,0x61,0xee = vmul.f64 d16, d17, d16
11 0xa1,0x4b,0x64,0xee = vmul.f64 d20, d20, d17
14 0xe0,0x0b,0x61,0xee = vnmul.f64 d16, d17, d16
16 0xe0,0x1b,0xf4,0xee = vcmpe.f64 d17, d16
18 0xc0,0x0b,0xf5,0xee = vcmpe.f64 d16, #0
20 0xe0,0x0b,0xf0,0xee = vabs.f64 d16, d16
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/ |
| D | float-intrinsics-double.ll | 8 declare double @llvm.sqrt.f64(double %Val)
12 ; HARD: vsqrt.f64 d0, d0
13 %1 = call double @llvm.sqrt.f64(double %a)
17 declare double @llvm.powi.f64(double %Val, i32 %power)
22 %1 = call double @llvm.powi.f64(double %a, i32 %b)
26 declare double @llvm.sin.f64(double %Val)
31 %1 = call double @llvm.sin.f64(double %a)
35 declare double @llvm.cos.f64(double %Val)
40 %1 = call double @llvm.cos.f64(double %a)
44 declare double @llvm.pow.f64(double %Val, double %power)
[all …]
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | float-intrinsics-double.ll | 8 declare double @llvm.sqrt.f64(double %Val)
12 ; HARD: vsqrt.f64 d0, d0
13 %1 = call double @llvm.sqrt.f64(double %a)
17 declare double @llvm.powi.f64(double %Val, i32 %power)
22 %1 = call double @llvm.powi.f64(double %a, i32 %b)
26 declare double @llvm.sin.f64(double %Val)
31 %1 = call double @llvm.sin.f64(double %a)
35 declare double @llvm.cos.f64(double %Val)
40 %1 = call double @llvm.cos.f64(double %a)
44 declare double @llvm.pow.f64(double %Val, double %power)
[all …]
|
| /external/llvm/test/CodeGen/WebAssembly/ |
| D | comparisons_f64.ll | 10 ; CHECK-NEXT: .param f64, f64{{$}}
12 ; CHECK-NEXT: f64.eq $push[[NUM0:[0-9]+]]=, $0, $0{{$}}
13 ; CHECK-NEXT: f64.eq $push[[NUM1:[0-9]+]]=, $1, $1{{$}}
23 ; CHECK-NEXT: .param f64, f64{{$}}
25 ; CHECK-NEXT: f64.ne $push[[NUM0:[0-9]+]]=, $0, $0{{$}}
26 ; CHECK-NEXT: f64.ne $push[[NUM1:[0-9]+]]=, $1, $1{{$}}
36 ; CHECK-NEXT: .param f64, f64{{$}}
38 ; CHECK-NEXT: f64.eq $push[[NUM:[0-9]+]]=, $0, $1{{$}}
47 ; CHECK: f64.ne $push[[NUM:[0-9]+]]=, $0, $1{{$}}
56 ; CHECK: f64.lt $push[[NUM:[0-9]+]]=, $0, $1{{$}}
[all …]
|
| D | f64.ll | 8 declare double @llvm.fabs.f64(double)
9 declare double @llvm.copysign.f64(double, double)
10 declare double @llvm.sqrt.f64(double)
11 declare double @llvm.ceil.f64(double)
12 declare double @llvm.floor.f64(double)
13 declare double @llvm.trunc.f64(double)
14 declare double @llvm.nearbyint.f64(double)
15 declare double @llvm.rint.f64(double)
16 declare double @llvm.fma.f64(double, double, double)
19 ; CHECK-NEXT: .param f64, f64{{$}}
[all …]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | simple-fp-encoding.s | 3 @ CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
4 vadd.f64 d16, d17, d16
9 @ CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee]
10 vsub.f64 d16, d17, d16
15 @ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
16 vdiv.f64 d16, d17, d16
21 @ CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee]
22 vmul.f64 d16, d17, d16
27 @ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
28 vnmul.f64 d16, d17, d16
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/WebAssembly/ |
| D | f64.ll | 8 declare double @llvm.fabs.f64(double)
9 declare double @llvm.copysign.f64(double, double)
10 declare double @llvm.sqrt.f64(double)
11 declare double @llvm.ceil.f64(double)
12 declare double @llvm.floor.f64(double)
13 declare double @llvm.trunc.f64(double)
14 declare double @llvm.nearbyint.f64(double)
15 declare double @llvm.rint.f64(double)
16 declare double @llvm.fma.f64(double, double, double)
19 ; CHECK-NEXT: .param f64, f64{{$}}
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | thumb-fp-armv8.txt | 4 # CHECK: vcvtt.f64.f16 d3, s1
7 # CHECK: vcvtt.f16.f64 s5, d12
10 # CHECK: vcvtb.f64.f16 d3, s1
13 # CHECK: vcvtb.f16.f64 s4, d1
17 # CHECK: vcvttge.f64.f16 d3, s1
21 # CHECK: vcvttgt.f16.f64 s5, d12
25 # CHECK: vcvtbeq.f64.f16 d3, s1
29 # CHECK: vcvtblt.f16.f64 s4, d1
36 # CHECK: vcvta.s32.f64 s2, d3
42 # CHECK: vcvtn.s32.f64 s6, d23
[all …]
|
| D | fp-armv8.txt | 4 # CHECK: vcvtt.f64.f16 d3, s1
7 # CHECK: vcvtt.f16.f64 s5, d12
10 # CHECK: vcvtb.f64.f16 d3, s1
13 # CHECK: vcvtb.f16.f64 s4, d1
16 # CHECK: vcvttge.f64.f16 d3, s1
19 # CHECK: vcvttgt.f16.f64 s5, d12
22 # CHECK: vcvtbeq.f64.f16 d3, s1
25 # CHECK: vcvtblt.f16.f64 s4, d1
32 # CHECK: vcvta.s32.f64 s2, d3
38 # CHECK: vcvtn.s32.f64 s6, d23
[all …]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb-fp-armv8.txt | 4 # CHECK: vcvtt.f64.f16 d3, s1
7 # CHECK: vcvtt.f16.f64 s5, d12
10 # CHECK: vcvtb.f64.f16 d3, s1
13 # CHECK: vcvtb.f16.f64 s4, d1
17 # CHECK: vcvttge.f64.f16 d3, s1
21 # CHECK: vcvttgt.f16.f64 s5, d12
25 # CHECK: vcvtbeq.f64.f16 d3, s1
29 # CHECK: vcvtblt.f16.f64 s4, d1
36 # CHECK: vcvta.s32.f64 s2, d3
42 # CHECK: vcvtn.s32.f64 s6, d23
[all …]
|