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Searched refs:fccmp (Results 1 – 25 of 33) sorted by relevance

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/external/llvm/test/CodeGen/AArch64/
Darm64-ccmp.ll137 ; CHECK: fccmp {{.*}}, #8, ge
453 ; CHECK-NEXT: fccmp d2, d3, #4, mi
454 ; CHECK-NEXT: fccmp d2, d3, #1, ne
468 ; CHECK-NEXT: fccmp d0, d1, #1, ne
469 ; CHECK-NEXT: fccmp d2, d3, #0, vc
483 ; CHECK-NEXT: fccmp d2, d3, #0, mi
484 ; CHECK-NEXT: fccmp d2, d3, #8, le
498 ; CHECK-NEXT: fccmp d0, d1, #8, le
499 ; CHECK-NEXT: fccmp d2, d3, #0, pl
513 ; CHECK-NEXT: fccmp d2, d3, #0, pl
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-ccmp.ll138 ; CHECK: fccmp {{.*}}, #8, ge
454 ; CHECK-NEXT: fccmp d2, d3, #4, mi
455 ; CHECK-NEXT: fccmp d2, d3, #1, ne
469 ; CHECK-NEXT: fccmp d0, d1, #1, ne
470 ; CHECK-NEXT: fccmp d2, d3, #0, vc
484 ; CHECK-NEXT: fccmp d2, d3, #0, mi
485 ; CHECK-NEXT: fccmp d2, d3, #8, le
499 ; CHECK-NEXT: fccmp d0, d1, #8, le
500 ; CHECK-NEXT: fccmp d2, d3, #0, pl
514 ; CHECK-NEXT: fccmp d2, d3, #0, pl
[all …]
Df16-instructions.ll475 ; CHECK-FP16-NEXT: fccmp h0, h2, #4, mi
/external/llvm/test/MC/AArch64/
Darm64-fp-encoding.s170 fccmp h1, h2, #0, eq
171 fccmp s1, s2, #0, eq
172 fccmp d1, d2, #0, eq define
177 ; FP16: fccmp h1, h2, #0, eq ; encoding: [0x20,0x04,0xe2,0x1e]
179 ; NO-FP16-NEXT: fccmp h1, h2, #0, eq
180 ; CHECK: fccmp s1, s2, #0, eq ; encoding: [0x20,0x04,0x22,0x1e]
181 ; CHECK: fccmp d1, d2, #0, eq ; encoding: [0x20,0x04,0x62,0x1e]
Dbasic-a64-diagnostics.s1560 fccmp s19, s5, #-1, lt
1561 fccmp s20, s7, #16, hs
1569 fccmp d19, d5, #-1, lt
1570 fccmp d20, d7, #16, hs
Dbasic-a64-instructions.s1786 fccmp s1, s31, #0, eq
1787 fccmp s3, s0, #15, hs
1788 fccmp s31, s15, #13, cs
1793 fccmp d9, d31, #0, le define
1794 fccmp d3, d0, #15, gt define
1795 fccmp d31, d5, #7, ne
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Darm64-fp-encoding.s170 fccmp h1, h2, #0, eq
171 fccmp s1, s2, #0, eq
172 fccmp d1, d2, #0, eq define
177 ; FP16: fccmp h1, h2, #0, eq ; encoding: [0x20,0x04,0xe2,0x1e]
179 ; NO-FP16-NEXT: fccmp h1, h2, #0, eq
180 ; CHECK: fccmp s1, s2, #0, eq ; encoding: [0x20,0x04,0x22,0x1e]
181 ; CHECK: fccmp d1, d2, #0, eq ; encoding: [0x20,0x04,0x62,0x1e]
Dbasic-a64-diagnostics.s1565 fccmp s19, s5, #-1, lt
1566 fccmp s20, s7, #16, hs
1574 fccmp d19, d5, #-1, lt
1575 fccmp d20, d7, #16, hs
Dbasic-a64-instructions.s1769 fccmp s1, s31, #0, eq
1770 fccmp s3, s0, #15, hs
1771 fccmp s31, s15, #13, cs
1776 fccmp d9, d31, #0, le define
1777 fccmp d3, d0, #15, gt define
1778 fccmp d31, d5, #7, ne
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-scalar-fp.txt143 # FP16: fccmp h1, h2, #0, eq
144 # CHECK: fccmp s1, s2, #0, eq
145 # CHECK: fccmp d1, d2, #0, eq
Dbasic-a64-instructions.txt1352 # CHECK: fccmp s1, s31, #0, eq
1353 # CHECK: fccmp s3, s0, #15, hs
1354 # CHECK: fccmp s31, s15, #13, hs
1359 # CHECK: fccmp d9, d31, #0, le
1360 # CHECK: fccmp d3, d0, #15, gt
1361 # CHECK: fccmp d31, d5, #7, ne
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-scalar-fp.txt143 # FP16: fccmp h1, h2, #0, eq
144 # CHECK: fccmp s1, s2, #0, eq
145 # CHECK: fccmp d1, d2, #0, eq
Dbasic-a64-instructions.txt1336 # CHECK: fccmp s1, s31, #0, eq
1337 # CHECK: fccmp s3, s0, #15, hs
1338 # CHECK: fccmp s31, s15, #13, hs
1343 # CHECK: fccmp d9, d31, #0, le
1344 # CHECK: fccmp d3, d0, #15, gt
1345 # CHECK: fccmp d31, d5, #7, ne
/external/capstone/suite/MC/AArch64/
Dbasic-a64-instructions.s.cs689 0x20,0x04,0x3f,0x1e = fccmp s1, s31, #0, eq
690 0x6f,0x24,0x20,0x1e = fccmp s3, s0, #15, hs
691 0xed,0x27,0x2f,0x1e = fccmp s31, s15, #13, hs
692 0x20,0xd5,0x7f,0x1e = fccmp d9, d31, #0, le
693 0x6f,0xc4,0x60,0x1e = fccmp d3, d0, #15, gt
694 0xe7,0x17,0x65,0x1e = fccmp d31, d5, #7, ne
/external/vixl/test/aarch64/
Dtest-disasm-aarch64.cc2950 COMPARE(fccmp(h8, h9, NoFlag, eq), "fccmp h8, h9, #nzcv, eq"); in TEST()
2951 COMPARE(fccmp(h10, h11, ZVFlag, ne), "fccmp h10, h11, #nZcV, ne"); in TEST()
2952 COMPARE(fccmp(h30, h16, NCFlag, pl), "fccmp h30, h16, #NzCv, pl"); in TEST()
2953 COMPARE(fccmp(h31, h31, NZCVFlag, le), "fccmp h31, h31, #NZCV, le"); in TEST()
2954 COMPARE(fccmp(s0, s1, NoFlag, eq), "fccmp s0, s1, #nzcv, eq"); in TEST()
2955 COMPARE(fccmp(s2, s3, ZVFlag, ne), "fccmp s2, s3, #nZcV, ne"); in TEST()
2956 COMPARE(fccmp(s30, s16, NCFlag, pl), "fccmp s30, s16, #NzCv, pl"); in TEST()
2957 COMPARE(fccmp(s31, s31, NZCVFlag, le), "fccmp s31, s31, #NZCV, le"); in TEST()
2958 COMPARE(fccmp(d4, d5, VFlag, gt), "fccmp d4, d5, #nzcV, gt"); in TEST()
2959 COMPARE(fccmp(d6, d7, NFlag, vs), "fccmp d6, d7, #Nzcv, vs"); in TEST()
[all …]
Dtest-cpu-features-aarch64.cc537 TEST_FP(fccmp_0, fccmp(d0, d1, NZCVFlag, pl))
538 TEST_FP(fccmp_1, fccmp(s0, s1, ZCVFlag, eq))
3386 TEST_FP_FPHALF(fccmp_0, fccmp(h0, h1, NCFlag, lt))
Dtest-trace-aarch64.cc409 __ fccmp(d6, d10, NoFlag, hs); in GenerateTestSequenceFP() local
410 __ fccmp(s29, s20, NZVFlag, ne); in GenerateTestSequenceFP() local
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h497 fccmp(fn, fm, nzcv, cond); in Fccmp()
Dassembler-arm64.h2485 void fccmp(const VRegister& vn, const VRegister& vm, StatusFlags nzcv,
/external/vixl/src/aarch64/
Dassembler-aarch64.h2276 void fccmp(const VRegister& vn,
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour333 0x~~~~~~~~~~~~~~~~ 1e6a24c0 fccmp d6, d10, #nzcv, hs
334 0x~~~~~~~~~~~~~~~~ 1e3417ad fccmp s29, s20, #NZcV, ne
Dlog-disasm333 0x~~~~~~~~~~~~~~~~ 1e6a24c0 fccmp d6, d10, #nzcv, hs
334 0x~~~~~~~~~~~~~~~~ 1e3417ad fccmp s29, s20, #NZcV, ne
Dlog-cpufeatures-custom332 0x~~~~~~~~~~~~~~~~ 1e6a24c0 fccmp d6, d10, #nzcv, hs ### {FP} ###
333 0x~~~~~~~~~~~~~~~~ 1e3417ad fccmp s29, s20, #NZcV, ne ### {FP} ###
Dlog-cpufeatures332 0x~~~~~~~~~~~~~~~~ 1e6a24c0 fccmp d6, d10, #nzcv, hs // Needs: FP
333 0x~~~~~~~~~~~~~~~~ 1e3417ad fccmp s29, s20, #NZcV, ne // Needs: FP
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md1686 void fccmp(const VRegister& vn,

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