| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | neon-scalar-cvt.s | 104 fcvtau h12, h13
105 fcvtau s12, s13
106 fcvtau d21, d14
|
| D | arm64-fp-encoding.s | 272 fcvtau w1, h2
273 fcvtau w1, s2
274 fcvtau w1, d2
275 fcvtau x1, h2
276 fcvtau x1, s2
277 fcvtau x1, d2
279 ; FP16: fcvtau w1, h2 ; encoding: [0x41,0x00,0xe5,0x1e]
281 ; NO-FP16-NEXT: fcvtau w1, h2
282 ; CHECK: fcvtau w1, s2 ; encoding: [0x41,0x00,0x25,0x1e]
283 ; CHECK: fcvtau w1, d2 ; encoding: [0x41,0x00,0x65,0x1e]
[all …]
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| D | neon-simd-misc.s | 658 fcvtau v4.4h, v0.4h
659 fcvtau v6.8h, v8.8h
660 fcvtau v6.4s, v8.4s
661 fcvtau v6.2d, v8.2d
662 fcvtau v4.2s, v0.2s
|
| D | fullfp16-neon-neg.s | 232 fcvtau h12, h13
366 fcvtau v4.4h, v0.4h
368 fcvtau v6.8h, v8.8h
|
| D | arm64-advsimd.s | 792 fcvtau.2s v0, v0
793 fcvtau.4s v0, v0
794 fcvtau.2d v0, v0
795 fcvtau s0, s0
796 fcvtau d0, d0 define
798 ; CHECK: fcvtau.2s v0, v0 ; encoding: [0x00,0xc8,0x21,0x2e]
799 ; CHECK: fcvtau.4s v0, v0 ; encoding: [0x00,0xc8,0x21,0x6e]
800 ; CHECK: fcvtau.2d v0, v0 ; encoding: [0x00,0xc8,0x61,0x6e]
801 ; CHECK: fcvtau s0, s0 ; encoding: [0x00,0xc8,0x21,0x7e]
802 ; CHECK: fcvtau d0, d0 ; encoding: [0x00,0xc8,0x61,0x7e]
|
| D | neon-diagnostics.s | 5876 fcvtau v0.16b, v31.16b
5877 fcvtau v2.8h, v4.8h
5878 fcvtau v1.8b, v9.8b
5879 fcvtau v13.4h, v21.4h
6961 fcvtau s0, d0
6962 fcvtau d0, s0 define
|
| D | basic-a64-instructions.s | 2098 fcvtau w29, s30
2099 fcvtau xzr, s0
2152 fcvtau w29, d30
2153 fcvtau xzr, d0
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-scalar-cvt.s | 104 fcvtau h12, h13
105 fcvtau s12, s13
106 fcvtau d21, d14
|
| D | arm64-fp-encoding.s | 272 fcvtau w1, h2
273 fcvtau w1, s2
274 fcvtau w1, d2
275 fcvtau x1, h2
276 fcvtau x1, s2
277 fcvtau x1, d2
279 ; FP16: fcvtau w1, h2 ; encoding: [0x41,0x00,0xe5,0x1e]
281 ; NO-FP16-NEXT: fcvtau w1, h2
282 ; CHECK: fcvtau w1, s2 ; encoding: [0x41,0x00,0x25,0x1e]
283 ; CHECK: fcvtau w1, d2 ; encoding: [0x41,0x00,0x65,0x1e]
[all …]
|
| D | neon-simd-misc.s | 658 fcvtau v4.4h, v0.4h
659 fcvtau v6.8h, v8.8h
660 fcvtau v6.4s, v8.4s
661 fcvtau v6.2d, v8.2d
662 fcvtau v4.2s, v0.2s
|
| D | fullfp16-neon-neg.s | 232 fcvtau h12, h13
366 fcvtau v4.4h, v0.4h
368 fcvtau v6.8h, v8.8h
|
| D | arm64-advsimd.s | 792 fcvtau.2s v0, v0
793 fcvtau.4s v0, v0
794 fcvtau.2d v0, v0
795 fcvtau s0, s0
796 fcvtau d0, d0 define
798 ; CHECK: fcvtau.2s v0, v0 ; encoding: [0x00,0xc8,0x21,0x2e]
799 ; CHECK: fcvtau.4s v0, v0 ; encoding: [0x00,0xc8,0x21,0x6e]
800 ; CHECK: fcvtau.2d v0, v0 ; encoding: [0x00,0xc8,0x61,0x6e]
801 ; CHECK: fcvtau s0, s0 ; encoding: [0x00,0xc8,0x21,0x7e]
802 ; CHECK: fcvtau d0, d0 ; encoding: [0x00,0xc8,0x61,0x7e]
|
| D | neon-diagnostics.s | 5936 fcvtau v0.16b, v31.16b
5937 fcvtau v2.8h, v4.8h
5938 fcvtau v1.8b, v9.8b
5939 fcvtau v13.4h, v21.4h
7192 fcvtau s0, d0
7193 fcvtau d0, s0 define
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-cvt.ll | 48 ;CHECK: fcvtau w0, s0
50 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %A)
56 ;CHECK: fcvtau x0, s0
58 %tmp3 = call i64 @llvm.aarch64.neon.fcvtau.i64.f32(float %A)
64 ;CHECK: fcvtau w0, d0
66 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f64(double %A)
72 ;CHECK: fcvtau x0, d0
74 %tmp3 = call i64 @llvm.aarch64.neon.fcvtau.i64.f64(double %A)
78 declare i32 @llvm.aarch64.neon.fcvtau.i32.f32(float) nounwind readnone
79 declare i64 @llvm.aarch64.neon.fcvtau.i64.f32(float) nounwind readnone
[all …]
|
| D | round-conv.ll | 284 ; CHECK: fcvtau w0, s0
294 ; CHECK: fcvtau x0, s0
304 ; CHECK: fcvtau w0, d0
314 ; CHECK: fcvtau x0, d0
|
| D | arm64-vcvt.ll | 37 ;CHECK: fcvtau.2s v0, v0
39 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float> %A)
46 ;CHECK: fcvtau.4s v0, v0
48 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float> %A)
55 ;CHECK: fcvtau.2d v0, v0
57 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double> %A)
61 declare <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float>) nounwind readnone
62 declare <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float>) nounwind readnone
63 declare <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double>) nounwind readnone
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-cvt.ll | 48 ;CHECK: fcvtau w0, s0
50 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %A)
56 ;CHECK: fcvtau x0, s0
58 %tmp3 = call i64 @llvm.aarch64.neon.fcvtau.i64.f32(float %A)
64 ;CHECK: fcvtau w0, d0
66 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f64(double %A)
72 ;CHECK: fcvtau x0, d0
74 %tmp3 = call i64 @llvm.aarch64.neon.fcvtau.i64.f64(double %A)
78 declare i32 @llvm.aarch64.neon.fcvtau.i32.f32(float) nounwind readnone
79 declare i64 @llvm.aarch64.neon.fcvtau.i64.f32(float) nounwind readnone
[all …]
|
| D | fp16_intrinsic_scalar_1op.ll | 15 declare i64 @llvm.aarch64.neon.fcvtau.i64.f16(half)
16 declare i32 @llvm.aarch64.neon.fcvtau.i32.f16(half)
162 ; CHECK: fcvtau w0, h0
165 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtau.i32.f16(half %a)
172 ; CHECK: fcvtau x0, h0
175 %vcvtah_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtau.i64.f16(half %a)
|
| D | round-conv.ll | 284 ; CHECK: fcvtau w0, s0
294 ; CHECK: fcvtau x0, s0
304 ; CHECK: fcvtau w0, d0
314 ; CHECK: fcvtau x0, d0
|
| D | arm64-vcvt.ll | 37 ;CHECK: fcvtau.2s v0, v0
39 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float> %A)
46 ;CHECK: fcvtau.4s v0, v0
48 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float> %A)
55 ;CHECK: fcvtau.2d v0, v0
57 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double> %A)
61 declare <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float>) nounwind readnone
62 declare <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float>) nounwind readnone
63 declare <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double>) nounwind readnone
|
| /external/capstone/suite/MC/AArch64/ |
| D | neon-scalar-cvt.s.cs | 17 0xac,0xc9,0x21,0x7e = fcvtau s12, s13
18 0xd5,0xc9,0x61,0x7e = fcvtau d21, d14
|
| D | neon-simd-misc.s.cs | 192 0x06,0xc9,0x21,0x6e = fcvtau v6.4s, v8.4s
193 0x06,0xc9,0x61,0x6e = fcvtau v6.2d, v8.2d
194 0x04,0xc8,0x21,0x2e = fcvtau v4.2s, v0.2s
|
| D | basic-a64-instructions.s.cs | 827 0xdd,0x03,0x25,0x1e = fcvtau w29, s30
828 0x1f,0x00,0x25,0x9e = fcvtau xzr, s0
851 0xdd,0x03,0x65,0x1e = fcvtau w29, d30
852 0x1f,0x00,0x65,0x9e = fcvtau xzr, d0
|
| /external/vixl/doc/ |
| D | changelog.md | 99 `frinta`, `fcvtau` and `fcvtas`.
|
| /external/vixl/test/aarch64/ |
| D | test-cpu-features-aarch64.cc | 553 TEST_FP(fcvtau_0, fcvtau(w0, d1))
554 TEST_FP(fcvtau_1, fcvtau(w0, s1))
555 TEST_FP(fcvtau_2, fcvtau(x0, d1))
556 TEST_FP(fcvtau_3, fcvtau(x0, s1))
3131 TEST_FP_NEON(fcvtau_0, fcvtau(v0.V2S(), v1.V2S()))
3132 TEST_FP_NEON(fcvtau_1, fcvtau(v0.V4S(), v1.V4S()))
3133 TEST_FP_NEON(fcvtau_2, fcvtau(v0.V2D(), v1.V2D()))
3134 TEST_FP_NEON(fcvtau_3, fcvtau(s0, s1))
3135 TEST_FP_NEON(fcvtau_4, fcvtau(d0, d1))
3394 TEST_FP_FPHALF(fcvtau_0, fcvtau(w0, h1))
[all …]
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