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Searched refs:fcvtl2 (Results 1 – 25 of 39) sorted by relevance

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/external/llvm/test/CodeGen/AArch64/
Dfp16-v8-instructions.ll217 ; CHECK: fcvtl2 v1.4s, v0.8h
373 ; CHECK-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h
387 ; CHECK-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h
400 ; CHECK-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h
414 ; CHECK-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h
Darm64-vcvt_f32_su32.ll46 ; CHECK: fcvtl2 v0.4s, v0.8h
Darm64-vcvt_f.ll16 ; CHECK: fcvtl2 v0.2d, v0.4s
Dvector-fcopysign.ll153 ; CHECK-NEXT: fcvtl2 v4.2d, v2.4s
/external/capstone/suite/MC/AArch64/
Dneon-simd-misc.s.cs142 0x8c,0x78,0x21,0x4e = fcvtl2 v12.4s, v4.8h
143 0x91,0x7b,0x61,0x4e = fcvtl2 v17.2d, v28.4s
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-vcvt_f32_su32.ll46 ; CHECK: fcvtl2 v0.4s, v0.8h
Dfp16-v8-instructions.ll238 ; CHECK: fcvtl2 v1.4s, v0.8h
397 ; CHECK-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h
411 ; CHECK-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h
424 ; CHECK-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h
438 ; CHECK-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h
Darm64-vcvt_f.ll16 ; CHECK: fcvtl2 v0.2d, v0.4s
Dvector-fcopysign.ll153 ; CHECK-NEXT: fcvtl2 v4.2d, v2.4s
/external/llvm/test/MC/AArch64/
Dneon-simd-misc.s449 fcvtl2 v12.4s, v4.8h
450 fcvtl2 v17.2d, v28.4s
Darm64-advsimd.s806 fcvtl2 v3.4s, v7.8h
807 fcvtl2 v4.2d, v8.4s
811 ; CHECK: fcvtl2 v3.4s, v7.8h ; encoding: [0xe3,0x78,0x21,0x4e]
812 ; CHECK: fcvtl2 v4.2d, v8.4s ; encoding: [0x04,0x79,0x61,0x4e]
Dneon-diagnostics.s5834 fcvtl2 v9.4s, v1.4h
5835 fcvtl2 v0.2d, v1.2s
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-simd-misc.s449 fcvtl2 v12.4s, v4.8h
450 fcvtl2 v17.2d, v28.4s
Darm64-advsimd.s806 fcvtl2 v3.4s, v7.8h
807 fcvtl2 v4.2d, v8.4s
811 ; CHECK: fcvtl2 v3.4s, v7.8h ; encoding: [0xe3,0x78,0x21,0x4e]
812 ; CHECK: fcvtl2 v4.2d, v8.4s ; encoding: [0x04,0x79,0x61,0x4e]
Dneon-diagnostics.s5774 fcvtl2 v9.4s, v1.4h
5775 fcvtl2 v0.2d, v1.2s
/external/v8/src/arm64/
Dmacro-assembler-arm64.h1318 fcvtl2(vd, vn); in Fcvtl2()
Dsimulator-arm64.h1977 LogicVRegister fcvtl2(VectorFormat vform, LogicVRegister dst,
Dassembler-arm64.h2503 void fcvtl2(const VRegister& vd, const VRegister& vn);
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt556 # CHECK: fcvtl2 v0.4s, v0.8h
558 # CHECK: fcvtl2 v0.2d, v0.4s
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt556 # CHECK: fcvtl2 v0.4s, v0.8h
558 # CHECK: fcvtl2 v0.2d, v0.4s
/external/vixl/src/aarch64/
Dsimulator-aarch64.h2939 LogicVRegister fcvtl2(VectorFormat vform,
Dassembler-aarch64.h2311 void fcvtl2(const VRegister& vd, const VRegister& vn);
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour2219 0x~~~~~~~~~~~~~~~~ 4e6178c1 fcvtl2 v1.2d, v6.4s
2220 0x~~~~~~~~~~~~~~~~ 4e217938 fcvtl2 v24.4s, v9.8h
Dlog-disasm2219 0x~~~~~~~~~~~~~~~~ 4e6178c1 fcvtl2 v1.2d, v6.4s
2220 0x~~~~~~~~~~~~~~~~ 4e217938 fcvtl2 v24.4s, v9.8h
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc2570 __ fcvtl2(v1.V2D(), v6.V4S()); in GenerateTestSequenceNEONFP() local
2571 __ fcvtl2(v24.V4S(), v9.V8H()); in GenerateTestSequenceNEONFP() local

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