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Searched refs:fcvtxn (Results 1 – 25 of 52) sorted by relevance

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/external/llvm/test/CodeGen/AArch64/
Darm64-vcvtxd_f32_f64.ll3 define float @fcvtxn(double %a) {
4 ; CHECK-LABEL: fcvtxn:
5 ; CHECK: fcvtxn s0, d0
7 %vcvtxd.i = tail call float @llvm.aarch64.sisd.fcvtxn(double %a) nounwind
11 declare float @llvm.aarch64.sisd.fcvtxn(double) nounwind readnone
Darm64-vcvt_f.ll41 %vcvtx1.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
42 ; CHECK: fcvtxn
49 %vcvtx2.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
63 declare <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone
Darm64-vcvt.ll526 ;CHECK: fcvtxn v0.2s, v0.2d
528 %tmp3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A)
537 %tmp3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A)
542 declare <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-vcvtxd_f32_f64.ll3 define float @fcvtxn(double %a) {
4 ; CHECK-LABEL: fcvtxn:
5 ; CHECK: fcvtxn s0, d0
7 %vcvtxd.i = tail call float @llvm.aarch64.sisd.fcvtxn(double %a) nounwind
11 declare float @llvm.aarch64.sisd.fcvtxn(double) nounwind readnone
Darm64-vcvt_f.ll41 %vcvtx1.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
42 ; CHECK: fcvtxn
49 %vcvtx2.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
63 declare <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone
Darm64-vcvt.ll526 ;CHECK: fcvtxn v0.2s, v0.2d
528 %tmp3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A)
537 %tmp3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A)
542 declare <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone
/external/capstone/suite/MC/AArch64/
Dneon-scalar-cvt.s.cs14 0xb6,0x69,0x61,0x7e = fcvtxn s22, d13
Dneon-simd-misc.s.cs139 0x04,0x68,0x61,0x2e = fcvtxn v4.2s, v0.2d
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s82 fcvtxn s22, d13
Dneon-simd-misc.s438 fcvtxn v4.2s, v0.2d
Dneon-diagnostics.s5760 fcvtxn v6.4s, v8.2d
6935 fcvtxn s0, s1
Darm64-advsimd.s866 fcvtxn v6.2s, v9.2d
873 ; CHECK: fcvtxn v6.2s, v9.2d ; encoding: [0x26,0x69,0x61,0x2e]
/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s82 fcvtxn s22, d13
Dneon-simd-misc.s438 fcvtxn v4.2s, v0.2d
Dneon-diagnostics.s5820 fcvtxn v6.4s, v8.2d
7166 fcvtxn s0, s1
Darm64-advsimd.s866 fcvtxn v6.2s, v9.2d
873 ; CHECK: fcvtxn v6.2s, v9.2d ; encoding: [0x26,0x69,0x61,0x2e]
/external/vixl/test/aarch64/
Dtest-simulator-aarch64.cc4792 DEFINE_TEST_NEON_2DIFF_FP_NARROW_2S(fcvtxn, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4839 CALL_TEST_NEON_HELPER_2DIFF(fcvtxn, S, D, kInputDoubleConversions); in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
/external/v8/src/arm64/
Dmacro-assembler-arm64.h1330 fcvtxn(vd, vn); in Fcvtxn()
Dsimulator-arm64.cc3586 fcvtxn(vf_fcvtn, rd, rn); in VisitNEON2RegMisc()
4987 fcvtxn(kFormatS, rd, rn); in VisitNEONScalar2RegMisc()
Dsimulator-arm64.h1983 LogicVRegister fcvtxn(VectorFormat vform, LogicVRegister dst,
Dassembler-arm64.h2512 void fcvtxn(const VRegister& vd, const VRegister& vn);
/external/vixl/src/aarch64/
Dsimulator-aarch64.cc3921 fcvtxn(vf_fcvtn, rd, rn); in VisitNEON2RegMisc()
5620 fcvtxn(kFormatS, rd, rn); in VisitNEONScalar2RegMisc()
Dsimulator-aarch64.h2948 LogicVRegister fcvtxn(VectorFormat vform,
Dassembler-aarch64.h2320 void fcvtxn(const VRegister& vd, const VRegister& vn);
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour417 0x~~~~~~~~~~~~~~~~ 7e61698c fcvtxn s12, d12
2243 0x~~~~~~~~~~~~~~~~ 2e61697d fcvtxn v29.2s, v11.2d

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