| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vcvt_f.ll | 51 ; CHECK: fcvtxn2
|
| D | arm64-vcvt.ll | 535 ;CHECK: fcvtxn2 v0.4s, v1.2d
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-vcvt_f.ll | 51 ; CHECK: fcvtxn2
|
| D | arm64-vcvt.ll | 535 ;CHECK: fcvtxn2 v0.4s, v1.2d
|
| /external/capstone/suite/MC/AArch64/ |
| D | neon-simd-misc.s.cs | 138 0x06,0x69,0x61,0x6e = fcvtxn2 v6.4s, v8.2d
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-misc.s | 437 fcvtxn2 v6.4s, v8.2d
|
| D | arm64-advsimd.s | 867 fcvtxn2 v7.4s, v8.2d
874 ; CHECK: fcvtxn2 v7.4s, v8.2d ; encoding: [0x07,0x69,0x61,0x6e]
|
| D | neon-diagnostics.s | 5821 fcvtxn2 v4.2s, v0.2d
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | neon-simd-misc.s | 437 fcvtxn2 v6.4s, v8.2d
|
| D | arm64-advsimd.s | 867 fcvtxn2 v7.4s, v8.2d
874 ; CHECK: fcvtxn2 v7.4s, v8.2d ; encoding: [0x07,0x69,0x61,0x6e]
|
| D | neon-diagnostics.s | 5761 fcvtxn2 v4.2s, v0.2d
|
| /external/v8/src/arm64/ |
| D | macro-assembler-arm64.h | 1334 fcvtxn2(vd, vn); in Fcvtxn2()
|
| D | simulator-arm64.h | 1985 LogicVRegister fcvtxn2(VectorFormat vform, LogicVRegister dst,
|
| D | assembler-arm64.h | 2515 void fcvtxn2(const VRegister& vd, const VRegister& vn);
|
| D | simulator-arm64.cc | 3584 fcvtxn2(vf_fcvtn, rd, rn); in VisitNEON2RegMisc()
|
| D | simulator-logic-arm64.cc | 3828 LogicVRegister Simulator::fcvtxn2(VectorFormat vform, LogicVRegister dst, in fcvtxn2() function in v8::internal::Simulator
|
| D | assembler-arm64.cc | 3172 void Assembler::fcvtxn2(const VRegister& vd, const VRegister& vn) { in fcvtxn2() function in v8::internal::Assembler
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 2951 LogicVRegister fcvtxn2(VectorFormat vform,
|
| D | assembler-aarch64.h | 2323 void fcvtxn2(const VRegister& vd, const VRegister& vn);
|
| D | macro-assembler-aarch64.h | 1398 fcvtxn2(vd, vn); in Fcvtxn2()
|
| D | simulator-aarch64.cc | 3919 fcvtxn2(vf_fcvtn, rd, rn); in VisitNEON2RegMisc()
|
| D | logic-aarch64.cc | 4908 LogicVRegister Simulator::fcvtxn2(VectorFormat vform, in fcvtxn2() function in vixl::aarch64::Simulator
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 1975 void fcvtxn2(const VRegister& vd, const VRegister& vn)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 564 # CHECK: fcvtxn2 v0.4s, v0.2d
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 564 # CHECK: fcvtxn2 v0.4s, v0.2d
|