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Searched refs:fcvtzs (Results 1 – 25 of 97) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/
Dfcvtzs.s10 fcvtzs z0.h, p0/m, z0.h label
16 fcvtzs z0.s, p0/m, z0.h label
22 fcvtzs z0.s, p0/m, z0.s label
28 fcvtzs z0.s, p0/m, z0.d label
34 fcvtzs z0.d, p0/m, z0.h label
40 fcvtzs z0.d, p0/m, z0.s label
46 fcvtzs z0.d, p0/m, z0.d label
62 fcvtzs z5.d, p0/m, z0.d label
74 fcvtzs z5.d, p0/m, z0.d label
Dfcvtzs-diagnostics.s3 fcvtzs z0.h, p0/m, z0.s label
8 fcvtzs z0.h, p0/m, z0.d label
17 fcvtzs z0.h, p8/m, z0.h label
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dcomplex-fp-to-int.ll6 ; CHECK: fcvtzs.2d v0, [[VAL64]]
23 ; CHECK: fcvtzs.2s v0, v0
31 ; CHECK: fcvtzs.2s v0, v0
39 ; CHECK: fcvtzs.2s v0, v0
47 ; CHECK: fcvtzs.2s v0, v0
55 ; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
73 ; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
82 ; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
91 ; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
109 ; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
[all …]
Darm64-convert-v4f64.ll6 ; CHECK-DAG: fcvtzs v[[LHS:[0-9]+]].2d, v0.2d
7 ; CHECK-DAG: fcvtzs v[[RHS:[0-9]+]].2d, v1.2d
18 ; CHECK-DAG: fcvtzs v[[CONV0:[0-9]+]].2d, v0.2d
19 ; CHECK-DAG: fcvtzs v[[CONV1:[0-9]+]].2d, v1.2d
20 ; CHECK-DAG: fcvtzs v[[CONV2:[0-9]+]].2d, v2.2d
21 ; CHECK-DAG: fcvtzs v[[CONV3:[0-9]+]].2d, v3.2d
Dfcvt_combine.ll5 ; CHECK: fcvtzs.2s v0, v0, #4
15 ; CHECK: fcvtzs.4s v0, v0, #3
25 ; CHECK: fcvtzs.2d v0, v0, #5
36 ; CHECK: fcvtzs.2d v0, v0
48 ; CHECK: fcvtzs.2s v0, v0, #4
61 ; CHECK: fcvtzs.2d v0, v0
126 ; CHECK: fcvtzs.2s v0, v0
137 ; CHECK: fcvtzs.2s v0, v0
147 ; CHECK: fcvtzs.2s v0, v0, #32
156 ; CHECK: fcvtzs.4s v0, v0, #2
Dfcvt-fixed.ll15 ; CHECK: fcvtzs {{w[0-9]+}}, {{s[0-9]+}}, #7
20 ; CHECK: fcvtzs {{w[0-9]+}}, {{s[0-9]+}}, #32
25 ; CHECK: fcvtzs {{x[0-9]+}}, {{s[0-9]+}}, #7
30 ; CHECK: fcvtzs {{x[0-9]+}}, {{s[0-9]+}}, #64
35 ; CHECK: fcvtzs {{w[0-9]+}}, {{d[0-9]+}}, #7
40 ; CHECK: fcvtzs {{w[0-9]+}}, {{d[0-9]+}}, #32
45 ; CHECK: fcvtzs {{x[0-9]+}}, {{d[0-9]+}}, #7
50 ; CHECK: fcvtzs {{x[0-9]+}}, {{d[0-9]+}}, #64
Darm64-cvt.ll328 ;CHECK: fcvtzs w0, s0
330 %tmp3 = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %A)
336 ;CHECK: fcvtzs x0, s0
338 %tmp3 = call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %A)
344 ;CHECK: fcvtzs w0, d0
346 %tmp3 = call i32 @llvm.aarch64.neon.fcvtzs.i32.f64(double %A)
352 ;CHECK: fcvtzs x0, d0
354 %tmp3 = call i64 @llvm.aarch64.neon.fcvtzs.i64.f64(double %A)
358 declare i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float) nounwind readnone
359 declare i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float) nounwind readnone
[all …]
Dfptouint-i8-zext.ll7 ; otherwise, fcvtzs must returns a value in [0, 256), which guarantees zext.
10 ; CHECK: fcvtzs [[A:w[0-9]+]], s0
Dfcvt-int.ll9 ; CHECK-DAG: fcvtzs [[SIG:w[0-9]+]], {{s[0-9]+}}
24 ; CHECK-DAG: fcvtzs [[SIG:w[0-9]+]], {{d[0-9]+}}
39 ; CHECK-DAG: fcvtzs [[SIG:x[0-9]+]], {{s[0-9]+}}
54 ; CHECK-DAG: fcvtzs [[SIG:x[0-9]+]], {{d[0-9]+}}
Darm64-vcvt_su32_f32.ll5 ; CHECK: fcvtzs.2s v0, v0
21 ; CHECK: fcvtzs.4s v0, v0
Dfp16_intrinsic_scalar_2op.ll181 ; CHECK: fcvtzs h0, h0, #1
192 ; CHECK: fcvtzs h0, h0, #16
203 ; CHECK: fcvtzs h0, h0, #1
213 ; CHECK: fcvtzs h0, h0, #16
223 ; CHECK: fcvtzs h0, h0, #1
233 ; CHECK: fcvtzs h0, h0, #32
/external/llvm/test/CodeGen/AArch64/
Dcomplex-fp-to-int.ll6 ; CHECK: fcvtzs.2d v0, [[VAL64]]
23 ; CHECK: fcvtzs.2s v0, v0
31 ; CHECK: fcvtzs.2s v0, v0
39 ; CHECK: fcvtzs.2s v0, v0
47 ; CHECK: fcvtzs.2s v0, v0
55 ; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
73 ; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
82 ; CHECK: fcvtzs.4s [[VAL64:v[0-9]+]], v0
91 ; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
109 ; CHECK: fcvtzs.2d [[VAL64:v[0-9]+]], v0
[all …]
Darm64-convert-v4f64.ll6 ; CHECK-DAG: fcvtzs v[[LHS:[0-9]+]].2d, v0.2d
7 ; CHECK-DAG: fcvtzs v[[RHS:[0-9]+]].2d, v1.2d
18 ; CHECK-DAG: fcvtzs v[[CONV0:[0-9]+]].2d, v0.2d
19 ; CHECK-DAG: fcvtzs v[[CONV1:[0-9]+]].2d, v1.2d
20 ; CHECK-DAG: fcvtzs v[[CONV2:[0-9]+]].2d, v2.2d
21 ; CHECK-DAG: fcvtzs v[[CONV3:[0-9]+]].2d, v3.2d
Dfcvt_combine.ll5 ; CHECK: fcvtzs.2s v0, v0, #4
15 ; CHECK: fcvtzs.4s v0, v0, #3
25 ; CHECK: fcvtzs.2d v0, v0, #5
36 ; CHECK: fcvtzs.2d v0, v0
48 ; CHECK: fcvtzs.2s v0, v0, #4
61 ; CHECK: fcvtzs.2d v0, v0
127 ; CHECK: fcvtzs.2s v0, v0
138 ; CHECK: fcvtzs.2s v0, v0
148 ; CHECK: fcvtzs.2s v0, v0, #32
157 ; CHECK: fcvtzs.4s v0, v0, #2
Dfcvt-fixed.ll15 ; CHECK: fcvtzs {{w[0-9]+}}, {{s[0-9]+}}, #7
20 ; CHECK: fcvtzs {{w[0-9]+}}, {{s[0-9]+}}, #32
25 ; CHECK: fcvtzs {{x[0-9]+}}, {{s[0-9]+}}, #7
30 ; CHECK: fcvtzs {{x[0-9]+}}, {{s[0-9]+}}, #64
35 ; CHECK: fcvtzs {{w[0-9]+}}, {{d[0-9]+}}, #7
40 ; CHECK: fcvtzs {{w[0-9]+}}, {{d[0-9]+}}, #32
45 ; CHECK: fcvtzs {{x[0-9]+}}, {{d[0-9]+}}, #7
50 ; CHECK: fcvtzs {{x[0-9]+}}, {{d[0-9]+}}, #64
Darm64-cvt.ll328 ;CHECK: fcvtzs w0, s0
330 %tmp3 = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %A)
336 ;CHECK: fcvtzs x0, s0
338 %tmp3 = call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %A)
344 ;CHECK: fcvtzs w0, d0
346 %tmp3 = call i32 @llvm.aarch64.neon.fcvtzs.i32.f64(double %A)
352 ;CHECK: fcvtzs x0, d0
354 %tmp3 = call i64 @llvm.aarch64.neon.fcvtzs.i64.f64(double %A)
358 declare i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float) nounwind readnone
359 declare i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float) nounwind readnone
[all …]
Dfcvt-int.ll9 ; CHECK-DAG: fcvtzs [[SIG:w[0-9]+]], {{s[0-9]+}}
24 ; CHECK-DAG: fcvtzs [[SIG:w[0-9]+]], {{d[0-9]+}}
39 ; CHECK-DAG: fcvtzs [[SIG:x[0-9]+]], {{s[0-9]+}}
54 ; CHECK-DAG: fcvtzs [[SIG:x[0-9]+]], {{d[0-9]+}}
Darm64-vcvt_su32_f32.ll5 ; CHECK: fcvtzs.2s v0, v0
21 ; CHECK: fcvtzs.4s v0, v0
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s57 fcvtzs h21, h12, #1
58 fcvtzs s21, s12, #1
59 fcvtzs d21, d12, #1
194 fcvtzs h12, h13
195 fcvtzs s12, s13
196 fcvtzs d21, d14
Darm64-fp-encoding.s398 fcvtzs w1, h2
399 fcvtzs w1, h2, #1
400 fcvtzs w1, s2
401 fcvtzs w1, s2, #1
402 fcvtzs w1, d2
403 fcvtzs w1, d2, #1
404 fcvtzs x1, h2
405 fcvtzs x1, h2, #1
406 fcvtzs x1, s2
407 fcvtzs x1, s2, #1
[all …]
Dneon-simd-shift.s428 fcvtzs v0.4h, v1.4h, #3
429 fcvtzs v0.8h, v1.8h, #3
430 fcvtzs v0.2s, v1.2s, #3
431 fcvtzs v0.4s, v1.4s, #3
432 fcvtzs v0.2d, v1.2d, #3
/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s57 fcvtzs h21, h12, #1
58 fcvtzs s21, s12, #1
59 fcvtzs d21, d12, #1
194 fcvtzs h12, h13
195 fcvtzs s12, s13
196 fcvtzs d21, d14
Darm64-fp-encoding.s398 fcvtzs w1, h2
399 fcvtzs w1, h2, #1
400 fcvtzs w1, s2
401 fcvtzs w1, s2, #1
402 fcvtzs w1, d2
403 fcvtzs w1, d2, #1
404 fcvtzs x1, h2
405 fcvtzs x1, h2, #1
406 fcvtzs x1, s2
407 fcvtzs x1, s2, #1
[all …]
Dneon-simd-shift.s428 fcvtzs v0.4h, v1.4h, #3
429 fcvtzs v0.8h, v1.8h, #3
430 fcvtzs v0.2s, v1.2s, #3
431 fcvtzs v0.4s, v1.4s, #3
432 fcvtzs v0.2d, v1.2d, #3
/external/capstone/suite/MC/AArch64/
Dneon-scalar-cvt.s.cs10 0x95,0xfd,0x3f,0x5f = fcvtzs s21, s12, #1
11 0x95,0xfd,0x7f,0x5f = fcvtzs d21, d12, #1
31 0xac,0xb9,0xa1,0x5e = fcvtzs s12, s13
32 0xd5,0xb9,0xe1,0x5e = fcvtzs d21, d14

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